MySQL in java

http://www.roseindia.net/jdbc/jdbc-mysql/mapping-mysql-data-types-in-java.shtml

mysql example site

http://www.mysqltutorial.org/

mysql c api example

MySQL C API proramming tutorial
About this tutorial

This is a C programming tutorial for the MySQL database. It covers the basics of MySQL programming with the C API.
About MySQL database

MySQL logo MySQL is a leading open source database management system. It is a multi user, multithreaded database management system. MySQL is especially popular on the web. It is a one of the parts of the very popular LAMP platform. Linux, Apache, MySQL, PHP. MySQL is owned by a swedish company called MySQL AB. This company and Trolltech are prominent open source companies. MySQL database is available on most important OS platforms. It runs under BSD Unix, Linux, Windows or Mac. Wikipedia and YouTube use MySQL. These sites manage millions of queries each day. MySQL comes in two versions. MySQL server system and MySQL embedded system.
First example

Our first example will test one MySQL function call.

#include my_global.h
#include mysql.h

int main(int argc, char **argv)
{
printf("MySQL client version: %s\n", mysql_get_client_info());
}

The mysql_get_client_info() shows the MySQL client version.

gcc version.c -o version `mysql_config --cflags --libs`

Here is how we compile the code example.

$ ./version
MySQL client version: 5.0.38

#include
#include

We include necessary header files. mysql.h is the most important header file for MySQL function calls. my_global.h includes some global declarations a functions. Among other thing, it includes the standard input/output header file.

printf("MySQL client version: %s\n", mysql_get_client_info());

This code line outputs the version of the MySQL client. For this, we use the mysql_get_client_info() function call.
Creating a database

The next code example will create a database.

#include
#include

int main(int argc, char **argv)
{

MYSQL *conn;

conn = mysql_init(NULL);

if (conn == NULL) {
printf("Error %u: %s\n", mysql_errno(conn), mysql_error(conn));
exit(1);
}

if (mysql_real_connect(conn, "localhost", "zetcode", "passwd", NULL, 0, NULL, 0) == NULL) {
printf("Error %u: %s\n", mysql_errno(conn), mysql_error(conn));
exit(1);
}

if (mysql_query(conn, "create database testdb")) {
printf("Error %u: %s\n", mysql_errno(conn), mysql_error(conn));
exit(1);
}


mysql_close(conn);

}

The code example connects to the MySQL database system and creates a new database called testdb.

mysql> show databases;
+--------------------+
| Database |
+--------------------+
| information_schema |
| mysql |
| testdb |
+--------------------+
3 rows in set (0.00 sec)

This is the proof, that the database was created.

We include error checking in this example. It is important to check for possible errors. Database programming is a field, where many things might go wrong. For clarity reasons, later examples will be without error checking. I suppose that it is clear for everyone, that it is every programmers responsibility to do error checking.

The code example can be divided into these parts.

* Initiation of a connection handle structure
* Creation of a connection
* Execution of a query
* Closing of the connection

MYSQL *conn;

We declare a pointer to a MYSQL structure. This structure will serve as a connection handler.

conn = mysql_init(NULL);

The mysql_init() function obtains a connection handler.

if (conn == NULL) {
printf("Error %u: %s\n", mysql_errno(conn), mysql_error(conn));
exit(1);
}

We check the return value. If the mysql_init() function fails, we print the error message and terminate the application.

if (mysql_real_connect(conn, "localhost", "zetcode", "passwd", NULL, 0, NULL, 0) == NULL) {
printf("Error %u: %s\n", mysql_errno(conn), mysql_error(conn));
exit(1);
}

The mysql_real_connect() function establishes a connection to the database. We provide connection handler, host name, user name and passwor parameters to the function. The other four parameters are the database name, port number, unix socket and finally the client flag.

if (mysql_query(conn, "create database testdb")) {
printf("Error %u: %s\n", mysql_errno(conn), mysql_error(conn));
exit(1);
}

The mysql_query() executes the SQL statement. In our case, the statement creates a new database.

mysql_close(conn);

Finally, we close the database connection.
Creating and populating a table

The next code example will create a table and insert some data into it.

#include
#include

int main(int argc, char **argv)
{

MYSQL *conn;

conn = mysql_init(NULL);
mysql_real_connect(conn, "localhost", "zetcode", "passwd", "testdb", 0, NULL, 0);

mysql_query(conn, "CREATE TABLE writers(name VARCHAR(25))");

mysql_query(conn, "INSERT INTO writers VALUES('Leo Tolstoy')");
mysql_query(conn, "INSERT INTO writers VALUES('Jack London')");
mysql_query(conn, "INSERT INTO writers VALUES('Honore de Balzac')");
mysql_query(conn, "INSERT INTO writers VALUES('Lion Feuchtwanger')");
mysql_query(conn, "INSERT INTO writers VALUES('Emile Zola')");

mysql_close(conn);

}

We don't use any new MySQL function call here. We use mysql_query() function call to both create a table and insert data into it.

mysql_real_connect(conn, "localhost", "zetcode", "passwd", "testdb", 0, NULL, 0);

We connect to testdb database. The user name is zetcode and password is passwd.

mysql_query(conn, "CREATE TABLE writers(name VARCHAR(25))");

Here we create a table named writers. It has one varchar column.

mysql_query(conn, "INSERT INTO writers VALUES('Leo Tolstoy')");

We insert one writer name into the writers table.

mysql> show tables;
+------------------+
| Tables_in_testdb |
+------------------+
| writers |
+------------------+
1 row in set (0.00 sec)


We show tables in the database.

mysql> select * from writers;
+-------------------+
| name |
+-------------------+
| Leo Tolstoy |
| Jack London |
| Honore de Balzac |
| Lion Feuchtwanger |
| Emile Zola |
+-------------------+
5 rows in set (0.00 sec)

We select all data from the table.
Retrieving data from the database

In the next example, we will retrieva data from a table.

Steps:

* Create a connection
* Execute query
* Get the result set
* Fetch all available rows
* Free the result set

#include
#include

int main(int argc, char **argv)
{

MYSQL *conn;
MYSQL_RES *result;
MYSQL_ROW row;
int num_fields;
int i;

conn = mysql_init(NULL);
mysql_real_connect(conn, "localhost", "zetcode", "passwd", "testdb", 0, NULL, 0);

mysql_query(conn, "SELECT * FROM writers");
result = mysql_store_result(conn);

num_fields = mysql_num_fields(result);

while ((row = mysql_fetch_row(result)))
{
for(i = 0; i < num_fields; i++)
{
printf("%s ", row[i] ? row[i] : "NULL");
}
printf("\n");
}

mysql_free_result(result);
mysql_close(conn);

}

The example prints all names from the writers table.

$ ./select
Leo Tolstoy
Jack London
Honore de Balzac
Lion Feuchtwanger
Emile Zola

mysql_query(conn, "SELECT * FROM writers");

We execute the query, that will retrieve all names from the writers database.

result = mysql_store_result(conn);

We get the result set.

num_fields = mysql_num_fields(result);

We get the number of fields in the table.

while ((row = mysql_fetch_row(result)))
{
for(i = 0; i < num_fields; i++)
{
printf("%s ", row[i] ? row[i] : "NULL");
}
printf("\n");
}

We fetch the rows and print them to the screen.

mysql_free_result(result);

We free the resources.
Column headers

In the next example, we will retrieve data and show the their column names from the table.

For this, we will create a new table friends.

mysql> create table friends (id int not null primary key auto_increment,
name varchar(20), age int);

mysql> insert into friends(name, age) values('Tom', 25);
mysql> insert into friends(name, age) values('Elisabeth', 32);
mysql> insert into friends(name, age) values('Jane', 22);
mysql> insert into friends(name, age) values('Luke', 28);

We insert some data into the table.

#include
#include

int main(int argc, char **argv)
{

MYSQL *conn;
MYSQL_RES *result;
MYSQL_ROW row;
MYSQL_FIELD *field;

int num_fields;
int i;

conn = mysql_init(NULL);
mysql_real_connect(conn, "localhost", "zetcode", "passwd", "testdb", 0, NULL, 0);

mysql_query(conn, "SELECT * FROM friends");
result = mysql_store_result(conn);

num_fields = mysql_num_fields(result);

while ((row = mysql_fetch_row(result)))
{
for(i = 0; i < num_fields; i++)
{
if (i == 0) {
while(field = mysql_fetch_field(result)) {
printf("%s ", field->name);
}
printf("\n");
}
printf("%s ", row[i] ? row[i] : "NULL");
}
}
printf("\n");

mysql_free_result(result);
mysql_close(conn);
}

The example is similar to the previous one. It just adds column header names to it.

while(field = mysql_fetch_field(result)) {
printf("%s ", field->name);
}

The mysql_fetch_field() call returns a MYSQL_FIELD structure. We get the column header names from this structure.

$ ./headers
id name age
1 Tom 25
2 Elisabeth 32
3 Jane 22
4 Luke 28

And this is the output of our program.
Inserting images into MySQL database

Some people prefer to put their images into the database, some prefer to keep them on the file system for their applications. Technical difficulties arise when we work with millions of images. Images are binary data. MySQL database has a special data type to store binary data called BLOB (Binary Large Object).

mysql> describe images;
+-------+------------+------+-----+---------+-------+
| Field | Type | Null | Key | Default | Extra |
+-------+------------+------+-----+---------+-------+
| id | int(11) | NO | PRI | | |
| data | mediumblob | YES | | NULL | |
+-------+------------+------+-----+---------+-------+
2 rows in set (0.00 sec)

This is the table, that we will use in our example. It can be created by the following SQL statement.

create table images(id int not null primary key, data mediumblob);

#include
#include

int main(int argc, char **argv)
{
MYSQL *conn;

int len, size;
char data[1000*1024];
char chunk[2*1000*1024+1];
char query[1024*5000];

FILE *fp;

conn = mysql_init(NULL);
mysql_real_connect(conn, "localhost", "zetcode", "passwd", "testdb", 0, NULL, 0);

fp = fopen("image.png", "rb");
size = fread(data, 1, 1024*1000, fp);

mysql_real_escape_string(conn, chunk, data, size);

char *stat = "INSERT INTO images(id, data) VALUES('1', '%s')";
len = snprintf(query, sizeof(stat)+sizeof(chunk) , stat, chunk);

mysql_real_query(conn, query, len);

fclose(fp);
mysql_close(conn);
}

In this example, we will insert one image into the images table. The image can be max 1 MB.

fp = fopen("image.png", "rb");
size = fread(data, 1, 1024*1000, fp);

Here we open the image and read it into the data array.

mysql_real_escape_string(conn, chunk, data, size);

Binary data can obtain special characters, that might cause troubles in the statements. We must escape them. The mysql_real_escape_string() puts the encoded data into the chunk array. In theory, every character might be a special character. That's why the chunk array two times as big as the data array. The function also adds a terminating null character.

char *stat = "INSERT INTO images(id, data) VALUES('1', '%s')";
len = snprintf(query, sizeof(stat)+sizeof(chunk) , stat, chunk);

These two code lines prepare the MySQL query.

mysql_real_query(conn, query, len);

Finally, we execute the query.
Selecting images from MySQL database

In the previous example, we have inserted an image into the database. In the following example, we will select the inserted image back from the database.

#include
#include

int main(int argc, char **argv)
{
MYSQL *conn;
MYSQL_RES *result;
MYSQL_ROW row;

unsigned long *lengths;
FILE *fp;

conn = mysql_init(NULL);
mysql_real_connect(conn, "localhost", "zetcode", "passwd", "testdb", 0, NULL, 0);

fp = fopen("image.png", "wb");

mysql_query(conn, "SELECT data FROM images WHERE id=1");
result = mysql_store_result(conn);

row = mysql_fetch_row(result);
lengths = mysql_fetch_lengths(result);

fwrite(row[0], lengths[0], 1, fp);
mysql_free_result(result);

fclose(fp);
mysql_close(conn);
}

In this example, we will create an image file from the database.

fp = fopen("image.png", "wb");

We open a file for writing.

mysql_query(conn, "SELECT data FROM images WHERE id=1");

We select an image with id 1.

row = mysql_fetch_row(result);

The row contains raw data.

lengths = mysql_fetch_lengths(result);

We get the length of the image.

fwrite(row[0], lengths[0], 1, fp);

We create the image file using the fwrite() standard function call.

SQL: enable remote access

By default, MySQL database server remote access disabled for security reasons. However, some time you need to provide the remote access to database server from home or from web server.

Solution1

Step # 1: Login over ssh

First, login over ssh to remote MySQL database server

Step # 2: Enable networking

Once connected you need edit the mysql configuration file
my.cfg using text editor such as vi.

In Debian Linux file is located at /etc/mysql/my.cnf

# vi /etc/my.cnf

Step # 3: Once file open, locate line that read as [mysqld]

Make sure line skip-networking is commented (or remove line) and add following line

bind-address=YOUR-SERVER-IP

For example, if your MySQL server IP is 172.20.5.2 then entire block should be look like as follows:

[mysqld]
user = mysql
pid-file = /var/run/mysqld/mysqld.pid
socket = /var/run/mysqld/mysqld.sock
port = 3306
basedir = /usr
datadir = /var/lib/mysql
tmpdir = /tmp
language = /usr/share/mysql/English
bind-address = 172.20.5.2

# skip-networking
....
..
....

Where,

bind-address : IP address to bind to.
skip-networking : Don’t listen for TCP/IP connections at all. All interaction with mysqld must be made via Unix sockets. This option is highly recommended for systems where only local requests are allowed. Since you need to allow remote connection this line should removed from file or put it in comment state.

Step# 4 Save and Close the file.

Restart your mysql service to take change in effect

# /etc/init.d/mysql restart

Step # 5 Grant access to remote IP address

# mysql -u root –p mysql

Grant access to new database

If you want to add new database called foo for user bar and remote IP 162.54.10.20 then you need to type following commands at mysql> prompt:

mysql> CREATE DATABASE foo;

mysql> GRANT ALL ON foo.* TO bar@'162.54.10.20' IDENTIFIED BY 'PASSWORD';

Grant access to existing database

Let us assume that you are always making connection from remote IP called 162.54.10.20 for database called webdb for user webadmin then you need to grant access to this IP address. At mysql> prompt type following command for existing database:

mysql> update db set Host='162.54.10.20' where Db='webdb';

mysql> update user set Host='162.54.10.20' where user='webadmin';

Step # 5: Logout of MySQL

Type exit command to logout mysql

mysql> exit

Step # 6: Test it

From remote system type command

$ mysql -u webadmin –h 172.20.5.2 –p

You can also use telnet to connect to port 3306 for testing purpose

$ telnet 172.20.5.2 3306

Solution 2

All you need to do is specify remote mysql host with –h option. For example to connect remote mysql server called server.test.com you need to type command as follows

$ mysql –u ruchi –h server.test.com -p

OR if you with to use MySQL server ip address (172.20.1.101)

what is volatile in c?

From somewhere in the internet...

8.4. Const and volatile

These are new in Standard C, although the idea of const has been borrowed from C++. Let us get one thing straight: the concepts of const and volatile are completely independent. A common misconception is to imagine that somehow const is the opposite of volatile and vice versa. They are unrelated and you should remember the fact.
Since const declarations are the simpler, we'll look at them first, but only after we have seen where both of these type qualifiers may be used. The complete list of relevant keywords is
char long float volatile
short signed double void
int unsigned const
In that list, const and volatile are type qualifiers, the rest are type specifiers. Various combinations of type specifiers are permitted:
char, signed char, unsigned char
int, signed int, unsigned int
short int, signed short int, unsigned short int
long int, signed long int, unsigned long int
float
double
long double
A few points should be noted. All declarations to do with an int will be signed anyway, so signed is redundant in that context. If any other type specifier or qualifier is present, then the int part may be dropped, as that is the default.
The keywords const and volatile can be applied to any declaration, including those of structures, unions, enumerated types or typedef names. Applying them to a declaration is called qualifying the declaration—that's why const and volatile are called type qualifiers, rather than type specifiers. Here are a few representative examples:
volatile i;
volatile int j;
const long q;
const volatile unsigned long int rt_clk;
struct{
const long int li;
signed char sc;
}volatile vs;
Don't be put off; some of them are deliberately complicated: what they mean will be explained later. Remember that they could also be further complicated by introducing storage class specifications as well! In fact, the truly spectacular
extern const volatile unsigned long int rt_clk;
is a strong possibility in some real-time operating system kernels.
8.4.1. Const

Let's look at what is meant when const is used. It's really quite simple: const means that something is not modifiable, so a data object that is declared with const as a part of its type specification must not be assigned to in any way during the run of a program. It is very likely that the definition of the object will contain an initializer (otherwise, since you can't assign to it, how would it ever get a value?), but this is not always the case. For example, if you were accessing a hardware port at a fixed memory address and promised only to read from it, then it would be declared to be const but not initialized.
Taking the address of a data object of a type which isn't const and putting it into a pointer to the const-qualified version of the same type is both safe and explicitly permitted; you will be able to use the pointer to inspect the object, but not modify it. Putting the address of a const type into a pointer to the unqualified type is much more dangerous and consequently prohibited (although you can get around this by using a cast). Here is an example:
#include
#include

main(){
int i;
const int ci = 123;

/* declare a pointer to a const.. */
const int *cpi;

/* ordinary pointer to a non-const */
int *ncpi;

cpi = &ci;
ncpi = &i;

/*
* this is allowed
*/
cpi = ncpi;

/*
* this needs a cast
* because it is usually a big mistake,
* see what it permits below.
*/
ncpi = (int *)cpi;

/*
* now to get undefined behaviour...
* modify a const through a pointer
*/
*ncpi = 0;

exit(EXIT_SUCCESS);
}
Example 8.3
As the example shows, it is possible to take the address of a constant object, generate a pointer to a non-constant, then use the new pointer. This is an error in your program and results in undefined behaviour.
The main intention of introducing const objects was to allow them to be put into read-only store, and to permit compilers to do extra consistency checking in a program. Unless you defeat the intent by doing naughty things with pointers, a compiler is able to check that const objects are not modified explicitly by the user.
An interesting extra feature pops up now. What does this mean?
char c;
char *const cp = &c;
It's simple really; cp is a pointer to a char, which is exactly what it would be if the const weren't there. The const means that cp is not to be modified, although whatever it points to can be—the pointer is constant, not the thing that it points to. The other way round is
const char *cp;
which means that now cp is an ordinary, modifiable pointer, but the thing that it points to must not be modified. So, depending on what you choose to do, both the pointer and the thing it points to may be modifiable or not; just choose the appropriate declaration.
8.4.2. Volatile

After const, we treat volatile. The reason for having this type qualifier is mainly to do with the problems that are encountered in real-time or embedded systems programming using C. Imagine that you are writing code that controls a hardware device by placing appropriate values in hardware registers at known absolute addresses.
Let's imagine that the device has two registers, each 16 bits long, at ascending memory addresses; the first one is the control and status register (csr) and the second is a data port. The traditional way of accessing such a device is like this:
/* Standard C example but without const or volatile */
/*
* Declare the device registers
* Whether to use int or short
* is implementation dependent
*/

struct devregs{
unsigned short csr; /* control & status */
unsigned short data; /* data port */
};

/* bit patterns in the csr */
#define ERROR 0x1
#define READY 0x2
#define RESET 0x4

/* absolute address of the device */
#define DEVADDR ((struct devregs *)0xffff0004)

/* number of such devices in system */
#define NDEVS 4

/*
* Busy-wait function to read a byte from device n.
* check range of device number.
* Wait until READY or ERROR
* if no error, read byte, return it
* otherwise reset error, return 0xffff
*/
unsigned int read_dev(unsigned devno){

struct devregs *dvp = DEVADDR + devno;

if(devno >= NDEVS)
return(0xffff);

while((dvp->csr & (READY | ERROR)) == 0)
; /* NULL - wait till done */

if(dvp->csr & ERROR){
dvp->csr = RESET;
return(0xffff);
}

return((dvp->data) & 0xff);
}
Example 8.4
The technique of using a structure declaration to describe the device register layout and names is very common practice. Notice that there aren't actually any objects of that type defined, so the declaration simply indicates the structure without using up any store.
To access the device registers, an appropriately cast constant is used as if it were pointing to such a structure, but of course it points to memory addresses instead.
However, a major problem with previous C compilers would be in the while loop which tests the status register and waits for the ERROR or READY bit to come on. Any self-respecting optimizing compiler would notice that the loop tests the same memory address over and over again. It would almost certainly arrange to reference memory once only, and copy the value into a hardware register, thus speeding up the loop. This is, of course, exactly what we don't want; this is one of the few places where we must look at the place where the pointer points, every time around the loop.
Because of this problem, most C compilers have been unable to make that sort of optimization in the past. To remove the problem (and other similar ones to do with when to write to where a pointer points), the keyword volatile was introduced. It tells the compiler that the object is subject to sudden change for reasons which cannot be predicted from a study of the program itself, and forces every reference to such an object to be a genuine reference.
Here is how you would rewrite the example, making use of const and volatile to get what you want.
/*
* Declare the device registers
* Whether to use int or short
* is implementation dependent
*/

struct devregs{
unsigned short volatile csr;
unsigned short const volatile data;
};

/* bit patterns in the csr */
#define ERROR 0x1
#define READY 0x2
#define RESET 0x4

/* absolute address of the device */
#define DEVADDR ((struct devregs *)0xffff0004)

/* number of such devices in system */
#define NDEVS 4

/*
* Busy-wait function to read a byte from device n.
* check range of device number.
* Wait until READY or ERROR
* if no error, read byte, return it
* otherwise reset error, return 0xffff
*/
unsigned int read_dev(unsigned devno){

struct devregs * const dvp = DEVADDR + devno;

if(devno >= NDEVS)
return(0xffff);

while((dvp->csr & (READY | ERROR)) == 0)
; /* NULL - wait till done */

if(dvp->csr & ERROR){
dvp->csr = RESET;
return(0xffff);
}

return((dvp->data) & 0xff);
}
Example 8.5
The rules about mixing volatile and regular types resemble those for const. A pointer to a volatile object can be assigned the address of a regular object with safety, but it is dangerous (and needs a cast) to take the address of a volatile object and put it into a pointer to a regular object. Using such a derived pointer results in undefined behaviour.
If an array, union or structure is declared with const or volatile attributes, then all of the members take on that attribute too. This makes sense when you think about it—how could a member of a const structure be modifiable?
That means that an alternative rewrite of the last example would be possible. Instead of declaring the device registers to be volatile in the structure, the pointer could have been declared to point to a volatile structure instead, like this:
struct devregs{
unsigned short csr; /* control & status */
unsigned short data; /* data port */
};
volatile struct devregs *const dvp=DEVADDR+devno;
Since dvp points to a volatile object, it not permitted to optimize references through the pointer. Our feeling is that, although this would work, it is bad style. The volatile declaration belongs in the structure: it is the device registers which are volatile and that is where the information should be kept; it reinforces the fact for a human reader.
So, for any object likely to be subject to modification either by hardware or asynchronous interrupt service routines, the volatile type qualifier is important.
Now, just when you thought that you understood all that, here comes the final twist. A declaration like this:
volatile struct devregs{
/* stuff */
}v_decl;
declares the type struct devregs and also a volatile-qualified object of that type, called v_decl. A later declaration like this
struct devregs nv_decl;
declares nv_decl which is not qualified with volatile! The qualification is not part of the type of struct devregs but applies only to the declaration of v_decl. Look at it this way round, which perhaps makes the situation more clear (the two declarations are the same in their effect):
struct devregs{
/* stuff */
}volatile v_decl;
If you do want to get a shorthand way of attaching a qualifier to another type, you can use typedef to do it:
struct x{
int a;
};
typedef const struct x csx;

csx const_sx;
struct x non_const_sx = {1};

const_sx = non_const_sx; /* error - attempt to modify a const */
8.4.2.1. Indivisible Operations

Those of you who are familiar with techniques that involve hardware interrupts and other ‘real time’ aspects of programming will recognise the need for volatile types. Related to this area is the need to ensure that accesses to data objects are ‘atomic’, or uninterruptable. To discuss this is any depth would take us beyond the scope of this book, but we can at least outline some of the issues.
Be careful not to assume that any operations written in C are uninterruptable. For example,
extern const volatile unsigned long realtimeclock;
could be a counter which is updated by a clock interrupt routine. It is essential to make it volatile because of the asynchronous updates to it, and it is marked const because it should not be changed by anything other than the interrupt routine. If the program accesses it like this:
unsigned long int time_of_day;

time_of_day = real_time_clock;
there may be a problem. What if, to copy one long into another, it takes several machine instructions to copy the two words making up real_time_clock and time_of_day? It is possible that an interrupt will occur in the middle of the assignment and that in the worst case, when the low-order word of real_time_clock is 0xffff and the high-order word is 0x0000, then the low-order word of time_of_day will receive 0xffff. The interrupt arrives and increments the low-order word of real_time_clock to 0x0 and then the high-order word to 0x1, then returns. The rest of the assignment then completes, with time_of_day ending up containing 0x0001ffff and real_time_clock containing the correct value, 0x00010000.
This whole class of problem is what is known as a critical region, and is well understood by those who regularly work in asynchronous environments. It should be understood that Standard C takes no special precautions to avoid these problems, and that the usual techniques should be employed.
The header ‘signal.h’ declares a type called sig_atomic_t which is guaranteed to be modifiable safely in the presence of asynchronous events. This means only that it can be modified by assigning a value to it; incrementing or decrementing it, or anything else which produces a new value depending on its previous value, is not safe.

Good links

http://www.gnu.org/software/gsl/ (including Optimization Package)

http://en.wikipedia.org/wiki/G%C3%B6del%27s_incompleteness_theorems (Godel's incompleteness theorems)

http://www.r-project.org/ (R - statistical tool)

http://lwn.net/Kernel/LDD3/ (Linux Device Driver 3rd edition - Free book)

http://perfeval.epfl.ch/ (Performance Evaluation)

http://code.google.com/p/otkpp/ (Nonlinear Optimization toolkit)

AR 5001 Known registers

+/*
+ * Known registers of the Atheros AR5001 Wireless LAN chipsets
+ * (AR5212/AR5311).
+ */
+
+#ifndef _AR5212_REG_H
+#define _AR5212_REG_H
+
+/*
+ * Command register
+ */
+#define AR5212_CR 0x0008
+#define AR5212_CR_RXE 0x00000004
+#define AR5212_CR_RXD 0x00000020
+#define AR5212_CR_SWI 0x00000040
+
+/*
+ * Receive queue descriptor pointer register
+ */
+#define AR5212_RXDP 0x000c
+
+/*
+ * Configuration and status register
+ */
+#define AR5212_CFG 0x0014
+#define AR5212_CFG_SWTD 0x00000001
+#define AR5212_CFG_SWTB 0x00000002
+#define AR5212_CFG_SWRD 0x00000004
+#define AR5212_CFG_SWRB 0x00000008
+#define AR5212_CFG_SWRG 0x00000010
+#define AR5212_CFG_ADHOC 0x00000020
+#define AR5212_CFG_PHY_OK 0x00000100
+#define AR5212_CFG_EEBS 0x00000200
+#define AR5212_CFG_CLKGD 0x00000400
+#define AR5212_CFG_PCI_THRES 0x00060000
+#define AR5212_CFG_PCI_THRES_S 17
+
+/*
+ * Interrupt enable register
+ */
+#define AR5212_IER 0x0024
+#define AR5212_IER_DISABLE 0x00000000
+#define AR5212_IER_ENABLE 0x00000001
+
+/*
+ * Transmit configuration register
+ */
+#define AR5212_TXCFG 0x0030
+#define AR5212_TXCFG_SDMAMR 0x00000007
+#define AR5212_TXCFG_B_MODE 0x00000008
+#define AR5212_TXCFG_TXFULL 0x000003f0
+#define AR5212_TXCFG_TXFULL_S 4
+#define AR5212_TXCFG_TXFULL_0B 0x00000000
+#define AR5212_TXCFG_TXFULL_64B 0x00000010
+#define AR5212_TXCFG_TXFULL_128B 0x00000020
+#define AR5212_TXCFG_TXFULL_192B 0x00000030
+#define AR5212_TXCFG_TXFULL_256B 0x00000040
+#define AR5212_TXCFG_TXCONT_ENABLE 0x00000080
+#define AR5212_TXCFG_JUMBO_TXE 0x00000400
+#define AR5212_TXCFG_RTSRND 0x00001000
+#define AR5212_TXCFG_FRMPAD_DIS 0x00002000
+#define AR5212_TXCFG_RDY_DIS 0x00004000
+
+/*
+ * Receive configuration register
+ */
+#define AR5212_RXCFG 0x0034
+#define AR5212_RXCFG_SDMAMW 0x00000007
+#define AR5311_RXCFG_DEFAULT_ANTENNA 0x00000008
+#define AR5212_RXCFG_ZLFDMA 0x00000010
+#define AR5212_RXCFG_JUMBO_RXE 0x00000020
+#define AR5212_RXCFG_JUMBO_WRAP 0x00000040
+
+/*
+ * MIB control register
+ */
+#define AR5212_MIBC 0x0040
+#define AR5212_MIBC_COW 0x00000001
+#define AR5212_MIBC_FMC 0x00000002
+#define AR5212_MIBC_CMC 0x00000004
+#define AR5212_MIBC_MCS 0x00000008
+
+/*
+ * Timeout prescale register
+ */
+#define AR5212_TOPS 0x0044
+#define AR5212_TOPS_M 0x0000ffff
+
+/*
+ * Receive timeout register (no frame received)
+ */
+#define AR5212_RXNOFRM 0x0048
+#define AR5212_RXNOFRM_M 0x000003ff
+
+/*
+ * Transmit timeout register (no frame sent)
+ */
+#define AR5212_TXNOFRM 0x004c
+#define AR5212_TXNOFRM_M 0x000003ff
+#define AR5212_TXNOFRM_QCU 0x000ffc00
+
+/*
+ * Receive frame gap timeout register
+ */
+#define AR5212_RPGTO 0x0050
+#define AR5212_RPGTO_M 0x000003ff
+
+/*
+ * Receive frame count limit register
+ */
+#define AR5212_RFCNT 0x0054
+#define AR5212_RFCNT_M 0x0000001f
+
+/*
+ * Misc settings register
+ */
+#define AR5212_MISC 0x0058
+#define AR5212_MISC_DMA_OBS_M 0x000001e0
+#define AR5212_MISC_DMA_OBS_S 5
+#define AR5212_MISC_MISC_OBS_M 0x00000e00
+#define AR5212_MISC_MISC_OBS_S 9
+#define AR5212_MISC_MAC_OBS_LSB_M 0x00007000
+#define AR5212_MISC_MAC_OBS_LSB_S 12
+#define AR5212_MISC_MAC_OBS_MSB_M 0x00038000
+#define AR5212_MISC_MAC_OBS_MSB_S 15
+
+/*
+ * Primary interrupt status register
+ */
+#define AR5212_PISR 0x0080
+#define AR5212_PISR_RXOK 0x00000001
+#define AR5212_PISR_RXDESC 0x00000002
+#define AR5212_PISR_RXERR 0x00000004
+#define AR5212_PISR_RXNOFRM 0x00000008
+#define AR5212_PISR_RXEOL 0x00000010
+#define AR5212_PISR_RXORN 0x00000020
+#define AR5212_PISR_TXOK 0x00000040
+#define AR5212_PISR_TXDESC 0x00000080
+#define AR5212_PISR_TXERR 0x00000100
+#define AR5212_PISR_TXNOFRM 0x00000200
+#define AR5212_PISR_TXEOL 0x00000400
+#define AR5212_PISR_TXURN 0x00000800
+#define AR5212_PISR_MIB 0x00001000
+#define AR5212_PISR_SWI 0x00002000
+#define AR5212_PISR_RXPHY 0x00004000
+#define AR5212_PISR_RXKCM 0x00008000
+#define AR5212_PISR_SWBA 0x00010000
+#define AR5212_PISR_BRSSI 0x00020000
+#define AR5212_PISR_BMISS 0x00040000
+#define AR5212_PISR_HIUERR 0x00080000
+#define AR5212_PISR_BNR 0x00100000
+#define AR5212_PISR_RXCHIRP 0x00200000
+#define AR5212_PISR_TIM 0x00800000
+#define AR5212_PISR_BCNMISC 0x00800000
+#define AR5212_PISR_GPIO 0x01000000
+#define AR5212_PISR_QCBRORN 0x02000000
+#define AR5212_PISR_QCBRURN 0x04000000
+#define AR5212_PISR_QTRIG 0x08000000
+
+/*
+ * Secondary interrupt status registers (0 - 4)
+ */
+#define AR5212_SISR0 0x0084
+#define AR5212_SISR0_QCU_TXOK 0x000003ff
+#define AR5212_SISR0_QCU_TXDESC 0x03ff0000
+
+#define AR5212_SISR1 0x0088
+#define AR5212_SISR1_QCU_TXERR 0x000003ff
+#define AR5212_SISR1_QCU_TXEOL 0x03ff0000
+
+#define AR5212_SISR2 0x008c
+#define AR5212_SISR2_QCU_TXURN 0x000003ff
+#define AR5212_SISR2_MCABT 0x00100000
+#define AR5212_SISR2_SSERR 0x00200000
+#define AR5212_SISR2_DPERR 0x00400000
+#define AR5212_SISR2_TIM 0x01000000
+#define AR5212_SISR2_CAB_END 0x02000000
+#define AR5212_SISR2_DTIM_SYNC 0x04000000
+#define AR5212_SISR2_BCN_TIMEOUT 0x08000000
+#define AR5212_SISR2_CAB_TIMEOUT 0x10000000
+#define AR5212_SISR2_DTIM 0x20000000
+
+#define AR5212_SISR3 0x0090
+#define AR5212_SISR3_QCBRORN 0x000003ff
+#define AR5212_SISR3_QCBRURN 0x03ff0000
+
+#define AR5212_SISR4 0x0094
+#define AR5212_SISR4_QTRIG 0x000003ff
+
+/*
+ * Shadow read-and-clear interrupt status registers
+ */
+#define AR5212_RAC_PISR 0x00c0
+#define AR5212_RAC_SISR0 0x00c4
+#define AR5212_RAC_SISR1 0x00c8
+#define AR5212_RAC_SISR2 0x00cc
+#define AR5212_RAC_SISR3 0c00d0
+#define AR5212_RAC_SISR4 0c00d4
+
+/*
+ * Primary interrupt mask register
+ */
+#define AR5212_PIMR 0x00a0
+#define AR5212_PIMR_RXOK 0x00000001
+#define AR5212_PIMR_RXDESC 0x00000002
+#define AR5212_PIMR_RXERR 0x00000004
+#define AR5212_PIMR_RXNOFRM 0x00000008
+#define AR5212_PIMR_RXEOL 0x00000010
+#define AR5212_PIMR_RXORN 0x00000020
+#define AR5212_PIMR_TXOK 0x00000040
+#define AR5212_PIMR_TXDESC 0x00000080
+#define AR5212_PIMR_TXERR 0x00000100
+#define AR5212_PIMR_TXNOFRM 0x00000200
+#define AR5212_PIMR_TXEOL 0x00000400
+#define AR5212_PIMR_TXURN 0x00000800
+#define AR5212_PIMR_MIB 0x00001000
+#define AR5212_PIMR_SWI 0x00002000
+#define AR5212_PIMR_RXPHY 0x00004000
+#define AR5212_PIMR_RXKCM 0x00008000
+#define AR5212_PIMR_SWBA 0x00010000
+#define AR5212_PIMR_BRSSI 0x00020000
+#define AR5212_PIMR_BMISS 0x00040000
+#define AR5212_PIMR_HIUERR 0x00080000
+#define AR5212_PIMR_BNR 0x00100000
+#define AR5212_PIMR_RXCHIRP 0x00200000
+#define AR5212_PIMR_TIM 0x00800000
+#define AR5212_PIMR_BCNMISC 0x00800000
+#define AR5212_PIMR_GPIO 0x01000000
+#define AR5212_PIMR_QCBRORN 0x02000000
+#define AR5212_PIMR_QCBRURN 0x04000000
+#define AR5212_PIMR_QTRIG 0x08000000
+
+/*
+ * Secondary interrupt mask registers (0 - 4)
+ */
+#define AR5212_SIMR0 0x00a4
+#define AR5212_SIMR0_QCU_TXOK 0x000003ff
+#define AR5212_SIMR0_QCU_TXOK_S 0
+#define AR5212_SIMR0_QCU_TXDESC 0x03ff0000
+#define AR5212_SIMR0_QCU_TXDESC_S 16
+
+#define AR5212_SIMR1 0x00a8
+#define AR5212_SIMR1_QCU_TXERR 0x000003ff
+#define AR5212_SIMR1_QCU_TXERR_S 0
+#define AR5212_SIMR1_QCU_TXEOL 0x03ff0000
+#define AR5212_SIMR1_QCU_TXEOL_S 16
+
+#define AR5212_SIMR2 0x00ac
+#define AR5212_SIMR2_QCU_TXURN 0x000003ff
+#define AR5212_SIMR2_QCU_TXURN_S 0
+#define AR5212_SIMR2_MCABT 0x00100000
+#define AR5212_SIMR2_SSERR 0x00200000
+#define AR5212_SIMR2_DPERR 0x00400000
+#define AR5212_SIMR2_TIM 0x01000000
+#define AR5212_SIMR2_CAB_END 0x02000000
+#define AR5212_SIMR2_DTIM_SYNC 0x04000000
+#define AR5212_SIMR2_BCN_TIMEOUT 0x08000000
+#define AR5212_SIMR2_CAB_TIMEOUT 0x10000000
+#define AR5212_SIMR2_DTIM 0x20000000
+
+#define AR5212_SIMR3 0x00b0
+#define AR5212_SIMR3_QCBRORN 0x000003ff
+#define AR5212_SIMR3_QCBRORN_S 0
+#define AR5212_SIMR3_QCBRURN 0x03ff0000
+#define AR5212_SIMR3_QCBRURN_S 16
+
+#define AR5212_SIMR4 0x00b4
+#define AR5212_SIMR4_QTRIG 0x000003ff
+#define AR5212_SIMR4_QTRIG_S 0
+
+/*
+ * Decompression mask registers
+ */
+#define AR5212_DCM_ADDR 0x0400
+#define AR5212_DCM_DATA 0x0404
+
+/*
+ * Decompression configuration registers
+ */
+#define AR5212_DCCFG 0x0420
+
+/*
+ * Compression configuration registers
+ */
+#define AR5212_CCFG 0x0600
+#define AR5212_CCFG_CUP 0x0604
+
+/*
+ * Compression performance counter registers
+ */
+#define AR5212_CPC0 0x0610
+#define AR5212_CPC1 0x0614
+#define AR5212_CPC2 0x0618
+#define AR5212_CPC3 0x061c
+#define AR5212_CPCORN 0x0620
+
+/*
+ * Queue control unit (QCU) registers (0 - 9)
+ */
+#define AR5212_QCU(_n, _a) (((_n) << 2) + _a)
+
+/*
+ * QCU Transmit descriptor pointer registers
+ */
+#define AR5212_QCU_TXDP(_n) AR5212_QCU(_n, 0x0800)
+
+/*
+ * QCU Transmit enable register
+ */
+#define AR5212_QCU_TXE 0x0840
+
+/*
+ * QCU Transmit disable register
+ */
+#define AR5212_QCU_TXD 0x0880
+
+/*
+ * QCU CBR configuration registers
+ */
+#define AR5212_QCU_CBRCFG(_n) AR5212_QCU(_n, 0x08c0)
+#define AR5212_QCU_CBRCFG_INTVAL 0x00ffffff
+#define AR5212_QCU_CBRCFG_INTVAL_S 0
+#define AR5212_QCU_CBRCFG_ORN_THRES 0xff000000
+#define AR5212_QCU_CBRCFG_ORN_THRES_S 24
+
+/*
+ * QCU Ready time configuration registers
+ */
+#define AR5212_QCU_RDYTIMECFG(_n) AR5212_QCU(_n, 0x0900)
+#define AR5212_QCU_RDYTIMECFG_INTVAL 0x00ffffff
+#define AR5212_QCU_RDYTIMECFG_INTVAL_S 0
+#define AR5212_QCU_RDYTIMECFG_DURATION 0x00ffffff
+#define AR5212_QCU_RDYTIMECFG_ENABLE 0x01000000
+
+/*
+ * QCU one shot arm set registers
+ */
+#define AR5212_QCU_ONESHOTARMS(_n) AR5212_QCU(_n, 0x0940)
+#define AR5212_QCU_ONESHOTARMS_M 0x0000ffff
+
+/*
+ * QCU one shot arm clear registers
+ */
+#define AR5212_QCU_ONESHOTARMC(_n) AR5212_QCU(_n, 0x0980)
+#define AR5212_QCU_ONESHOTARMC_M 0x0000ffff
+
+/*
+ * QCU misc registers
+ */
+#define AR5212_QCU_MISC(_n) AR5212_QCU(_n, 0x09c0)
+#define AR5212_QCU_MISC_FRSHED_M 0x0000000f
+#define AR5212_QCU_MISC_FRSHED_ASAP 0
+#define AR5212_QCU_MISC_FRSHED_CBR 1
+#define AR5212_QCU_MISC_FRSHED_DBA_GT 2
+#define AR5212_QCU_MISC_FRSHED_TIM_GT 3
+#define AR5212_QCU_MISC_FRSHED_BCN_SENT_GT 4
+#define AR5212_QCU_MISC_ONESHOT_ENABLE 0x00000010
+#define AR5212_QCU_MISC_CBREXP 0x00000020
+#define AR5212_QCU_MISC_CBREXP_BCN 0x00000040
+#define AR5212_QCU_MISC_BCN_ENABLE 0x00000080
+#define AR5212_QCU_MISC_CBR_THRES_ENABLE 0x00000100
+#define AR5212_QCU_MISC_TXE 0x00000200
+#define AR5212_QCU_MISC_CBR 0x00000400
+#define AR5212_QCU_MISC_DCU_EARLY 0x00000800
+
+/*
+ * QCU status registers
+ */
+#define AR5212_QCU_STS(_n) AR5212_QCU(_n, 0x0a00)
+#define AR5212_QCU_STS_FRMPENDCNT 0x00000003
+#define AR5212_QCU_STS_CBREXPCNT 0x0000ff00
+
+/*
+ * QCU ready time shutdown register
+ */
+#define AR5212_QCU_RDYTIMESHDN 0x0a40
+#define AR5212_QCU_RDYTIMESHDN_M 0x000003ff
+
+/*
+ * QCU compression buffer base registers
+ */
+#define AR5212_QCU_CBB_SELECT 0x0b00
+#define AR5212_QCU_CBB_ADDR 0x0b04
+
+/*
+ * QCU compression buffer configuration register
+ */
+#define AR5212_QCU_CBCFG 0x0b08
+
+/*
+ * DCF control unit (DCU) registers (0 - 9)
+ */
+#define AR5212_DCU(_n, _a) AR5212_QCU(_n, _a)
+
+/*
+ * DCU QCU mask registers
+ */
+#define AR5212_DCU_QCUMASK(_n) AR5212_DCU(_n, 0x1000)
+#define AR5212_DCU_QCUMASK_M 0x000003ff
+
+/*
+ * DCU local IFS settings register
+ */
+#define AR5212_DCU_LCL_IFS(_n) AR5212_DCU(_n, 0x1040)
+#define AR5212_DCU_LCL_IFS_CW_MIN 0x000003ff
+#define AR5212_DCU_LCL_IFS_CW_MIN_S 0
+#define AR5212_DCU_LCL_IFS_CW_MAX 0x000ffc00
+#define AR5212_DCU_LCL_IFS_CW_MAX_S 10
+#define AR5212_DCU_LCL_IFS_AIFS 0x0ff00000
+#define AR5212_DCU_LCL_IFS_AIFS_S 20
+
+/*
+ * DCU retry limit registers
+ */
+#define AR5212_DCU_RETRY_LMT(_n) AR5212_DCU(_n, 0x1080)
+#define AR5212_DCU_RETRY_LMT_SH_RETRY 0x0000000f
+#define AR5212_DCU_RETRY_LMT_SH_RETRY_S 0
+#define AR5212_DCU_RETRY_LMT_LG_RETRY 0x000000f0
+#define AR5212_DCU_RETRY_LMT_LG_RETRY_S 4
+#define AR5212_DCU_RETRY_LMT_SSH_RETRY 0x00003f00
+#define AR5212_DCU_RETRY_LMT_SSH_RETRY_S 8
+#define AR5212_DCU_RETRY_LMT_SLG_RETRY 0x000fc000
+#define AR5212_DCU_RETRY_LMT_SLG_RETRY_S 14
+
+/*
+ * DCU channel time registers
+ */
+#define AR5212_DCU_CHAN_TIME(_n) AR5212_DCU(_n, 0x10c0)
+#define AR5212_DCU_CHAN_TIME_DUR 0x000fffff
+#define AR5212_DCU_CHAN_TIME_DUR_S 0
+#define AR5212_DCU_CHAN_TIME_ENABLE 0x00100000
+
+/*
+ * DCU misc registers
+ */
+#define AR5212_DCU_MISC(_n) AR5212_DCU(_n, 0x1100)
+#define AR5212_DCU_MISC_BACKOFF 0x000007ff
+#define AR5212_DCU_MISC_BACKOFF_FRAG 0x00000200
+#define AR5212_DCU_MISC_HCFPOLL_ENABLE 0x00000800
+#define AR5212_DCU_MISC_BACKOFF_PERSIST 0x00001000
+#define AR5212_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000
+#define AR5212_DCU_MISC_VIRTCOL 0x0000c000
+#define AR5212_DCU_MISC_VIRTCOL_NORMAL 0
+#define AR5212_DCU_MISC_VIRTCOL_MODIFIED 1
+#define AR5212_DCU_MISC_VIRTCOL_IGNORE 2
+#define AR5212_DCU_MISC_BCN_ENABLE 0x00010000
+#define AR5212_DCU_MISC_ARBLOCK_CTL 0x00060000
+#define AR5212_DCU_MISC_ARBLOCK_CTL_S 17
+#define AR5212_DCU_MISC_ARBLOCK_CTL_NONE 0
+#define AR5212_DCU_MISC_ARBLOCK_CTL_INTFRM 1
+#define AR5212_DCU_MISC_ARBLOCK_CTL_GLOBAL 2
+#define AR5212_DCU_MISC_ARBLOCK_IGNORE 0x00080000
+#define AR5212_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000
+#define AR5212_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000
+#define AR5212_DCU_MISC_VIRT_COLL_POLICY 0x00400000
+#define AR5212_DCU_MISC_BLOWN_IFS_POLICY 0x00800000
+#define AR5212_DCU_MISC_SEQNUM_CTL 0x01000000
+
+/*
+ * DCU frame sequence number registers
+ */
+#define AR5212_DCU_SEQNUM(_n) AR5212_DCU(_n, 0x1140)
+#define AR5212_DCU_SEQNUM_M 0x00000fff
+/*
+ * DCU global IFS SIFS registers
+ */
+#define AR5212_DCU_GBL_IFS_SIFS 0x1030
+#define AR5212_DCU_GBL_IFS_SIFS_M 0x0000ffff
+
+/*
+ * DCU global IFS slot interval registers
+ */
+#define AR5212_DCU_GBL_IFS_SLOT 0x1070
+#define AR5212_DCU_GBL_IFS_SLOT_M 0x0000ffff
+
+/*
+ * DCU global IFS EIFS registers
+ */
+#define AR5212_DCU_GBL_IFS_EIFS 0x10b0
+#define AR5212_DCU_GBL_IFS_EIFS_M 0x0000ffff
+
+/*
+ * DCU global IFS misc registers
+ */
+#define AR5212_DCU_GBL_IFS_MISC 0x10f0
+#define AR5212_DCU_GBL_IFS_MISC_LFSR_SLICE 0x00000007
+#define AR5212_DCU_GBL_IFS_MISC_TURBO_MODE 0x00000008
+#define AR5212_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0
+#define AR5212_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00
+#define AR5212_DCU_GBL_IFS_MISC_DCU_ARB_DELAY 0x00300000
+
+/*
+ * DCU frame prefetch control register
+ */
+#define AR5212_DCU_FP 0x1230
+
+/*
+ * DCU transmit pause control/status register
+ */
+#define AR5212_DCU_TXP 0x1270
+#define AR5212_DCU_TXP_M 0x000003ff
+#define AR5212_DCU_TXP_STATUS 0x00010000
+
+/*
+ * DCU transmit filter register
+ */
+#define AR5212_DCU_TX_FILTER 0x1038
+
+/*
+ * DCU clear transmit filter register
+ */
+#define AR5212_DCU_TX_FILTER_CLR 0x143c
+
+/*
+ * DCU set transmit filter register
+ */
+#define AR5212_DCU_TX_FILTER_SET 0x147c
+
+/*
+ * DMA size definitions
+ */
+typedef enum {
+ AR5212_DMASIZE_4B = 0,
+ AR5212_DMASIZE_8B,
+ AR5212_DMASIZE_16B,
+ AR5212_DMASIZE_32B,
+ AR5212_DMASIZE_64B,
+ AR5212_DMASIZE_128B,
+ AR5212_DMASIZE_256B,
+ AR5212_DMASIZE_512B
+} ar5212_dmasize_t;
+
+/*
+ * Reset control register
+ */
+#define AR5212_RC 0x4000
+#define AR5212_RC_PCU 0x00000001
+#define AR5212_RC_BB 0x00000002
+#define AR5212_RC_PCI 0x00000010
+#define AR5212_RC_CHIP ( \
+ AR5212_RC_PCU | AR5212_RC_BB | AR5212_RC_PCI \
+)
+
+/*
+ * Sleep control register
+ */
+#define AR5212_SCR 0x4004
+#define AR5212_SCR_SLDUR 0x0000ffff
+#define AR5212_SCR_SLE 0x00030000
+#define AR5212_SCR_SLE_S 16
+#define AR5212_SCR_SLE_WAKE 0x00000000
+#define AR5212_SCR_SLE_SLP 0x00010000
+#define AR5212_SCR_SLE_ALLOW 0x00020000
+#define AR5212_SCR_SLE_UNITS 0x00000008
+
+/*
+ * Interrupt pending register
+ */
+#define AR5212_INTPEND 0x4008
+#define AR5212_INTPEND_M 0x00000001
+
+/*
+ * Sleep force register
+ */
+#define AR5212_SFR 0x400c
+#define AR5212_SFR_M 0x00000001
+
+/*
+ * PCI configuration register
+ */
+#define AR5212_PCICFG 0x4010
+#define AR5212_PCICFG_CLKRUNEN 0x00000004
+#define AR5212_PCICFG_EESIZE 0x00000018
+#define AR5212_PCICFG_EESIZE_S 3
+#define AR5212_PCICFG_EESIZE_4K 0
+#define AR5212_PCICFG_EESIZE_8K 1
+#define AR5212_PCICFG_EESIZE_16K 2
+#define AR5212_PCICFG_EESIZE_FAIL 3
+#define AR5212_PCICFG_LED 0x00000060
+#define AR5212_PCICFG_LED_NONE 0x00000000
+#define AR5212_PCICFG_LED_PEND 0x00000020
+#define AR5212_PCICFG_LED_ASSOC 0x00000040
+#define AR5212_PCICFG_BUS_SEL 0x00000380
+#define AR5212_PCICFG_CBEFIX_DIS 0x00000400
+#define AR5212_PCICFG_SL_INTEN 0x00000800
+#define AR5212_PCICFG_SL_INPEN 0x00002800
+#define AR5212_PCICFG_SPWR_DN 0x00010000
+#define AR5212_PCICFG_LEDMODE 0x000e0000
+#define AR5212_PCICFG_LEDMODE_PROP 0x00000000
+#define AR5212_PCICFG_LEDMODE_PROM 0x00020000
+#define AR5212_PCICFG_LEDMODE_PWR 0x00040000
+#define AR5212_PCICFG_LEDMODE_RAND 0x00060000
+#define AR5212_PCICFG_LEDBLINK 0x00700000
+#define AR5212_PCICFG_LEDBLINK_S 20
+#define AR5212_PCICFG_LEDSLOW 0x00800000
+
+/*
+ * "General Purpose Input/Output" (GPIO) control register
+ */
+#define AR5212_GPIOCR 0x4014
+#define AR5212_GPIOCR_INT_ENA 0x00008000
+#define AR5212_GPIOCR_INT_SELL 0x00000000
+#define AR5212_GPIOCR_INT_SELH 0x00010000
+#define AR5212_GPIOCR_NONE(n) (0 << ((n) * 2))
+#define AR5212_GPIOCR_OUT0(n) (1 << ((n) * 2))
+#define AR5212_GPIOCR_OUT1(n) (2 << ((n) * 2))
+#define AR5212_GPIOCR_ALL(n) (3 << ((n) * 2))
+#define AR5212_GPIOCR_INT_SEL(n) ((n) << 12)
+
+#define AR5212_NUM_GPIO 6
+
+/*
+ * "General Purpose Input/Output" (GPIO) data output register
+ */
+#define AR5212_GPIODO 0x4018
+
+/*
+ * "General Purpose Input/Output" (GPIO) data input register
+ */
+#define AR5212_GPIODI 0x401c
+#define AR5212_GPIODI_M 0x0000002f
+
+/*
+ * Silicon revision register
+ */
+#define AR5212_SREV 0x4020
+#define AR5212_SREV_M 0x000000ff
+#define AR5212_SREV_REVISION 0x0000000f
+#define AR5212_SREV_VERSION 0x000000f0
+
+/*
+ * EEPROM access registers
+ */
+#define AR5212_EEPROM_BASE 0x6000
+#define AR5212_EEPROM_DATA 0x6004
+#define AR5212_EEPROM_CMD 0x6008
+#define AR5212_EEPROM_CMD_READ 0x00000001
+#define AR5212_EEPROM_CMD_WRITE 0x00000002
+#define AR5212_EEPROM_CMD_RESET 0x00000004
+#define AR5212_EEPROM_STATUS 0x600c
+#define AR5212_EEPROM_STAT_RDERR 0x00000001
+#define AR5212_EEPROM_STAT_RDDONE 0x00000002
+#define AR5212_EEPROM_STAT_WRERR 0x00000004
+#define AR5212_EEPROM_STAT_WRDONE 0x00000008
+#define AR5212_EEPROM_CFG 0x6010
+
+/*
+ * PCU registers
+ */
+
+#define AR5212_PCU_MIN 0x8000
+#define AR5212_PCU_MAX 0x8fff
+
+/*
+ * First station id register (MAC address in lower 32 bits)
+ */
+#define AR5212_STA_ID0 0x8000
+
+/*
+ * Second station id register (MAC address in upper 16 bits)
+ */
+#define AR5212_STA_ID1 0x8004
+#define AR5212_STA_ID1_AP 0x00010000
+#define AR5212_STA_ID1_ADHOC 0x00020000
+#define AR5212_STA_ID1_PWR_SV 0x00040000
+#define AR5212_STA_ID1_NO_KEYSRCH 0x00080000
+#define AR5212_STA_ID1_PCF 0x00100000
+#define AR5212_STA_ID1_DEFAULT_ANTENNA 0x00200000
+#define AR5212_STA_ID1_DESC_ANTENNA 0x00400000
+#define AR5212_STA_ID1_RTS_DEFAULT_ANTENNA 0x00800000
+#define AR5212_STA_ID1_ACKCTS_6MB 0x01000000
+#define AR5212_STA_ID1_BASE_RATE_11B 0x02000000
+
+/*
+ * First BSSID register (MAC address, lower 32bits)
+ */
+#define AR5212_BSS_ID0 0x8008
+
+/*
+ * Second BSSID register (MAC address in upper 16 bits)
+ *
+ * AID: Association ID
+ */
+#define AR5212_BSS_ID1 0x800c
+#define AR5212_BSS_ID1_AID 0xffff0000
+#define AR5212_BSS_ID1_AID_S 16
+
+/*
+ * Backoff slot time register
+ */
+#define AR5212_SLOT_TIME 0x8010
+
+/*
+ * ACK/CTS timeout register
+ */
+#define AR5212_TIME_OUT 0x8014
+#define AR5212_TIME_OUT_ACK 0x00001fff
+#define AR5212_TIME_OUT_ACK_S 0
+#define AR5212_TIME_OUT_CTS 0x1fff0000
+#define AR5212_TIME_OUT_CTS_S 16
+
+/*
+ * RSSI threshold register
+ */
+#define AR5212_RSSI_THR 0x8018
+#define AR5212_RSSI_THR_M 0x000000ff
+#define AR5212_RSSI_THR_BMISS 0x0000ff00
+#define AR5212_RSSI_THR_BMISS_S 8
+
+/*
+ * Transmit latency register
+ */
+#define AR5212_USEC 0x801c
+#define AR5212_USEC_1 0x0000007f
+#define AR5212_USEC_1_S 0
+#define AR5212_USEC_32 0x00003f80
+#define AR5212_USEC_32_S 7
+#define AR5212_USEC_TX_LATENCY 0x007fc000
+#define AR5212_USEC_TX_LATENCY_S 14
+#define AR5212_USEC_RX_LATENCY 0x1f800000
+#define AR5212_USEC_RX_LATENCY_S 23
+#define AR5311_USEC_TX_LATENCY 0x000fc000
+#define AR5311_USEC_TX_LATENCY_S 14
+#define AR5311_USEC_RX_LATENCY 0x03f00000
+#define AR5311_USEC_RX_LATENCY_S 20
+
+/*
+ * PCU beacon control register
+ */
+#define AR5212_BEACON 0x8020
+#define AR5212_BEACON_PERIOD 0x0000ffff
+#define AR5212_BEACON_PERIOD_S 0
+#define AR5212_BEACON_TIM 0x007f0000
+#define AR5212_BEACON_TIM_S 16
+#define AR5212_BEACON_ENABLE 0x00800000
+#define AR5212_BEACON_RESET_TSF 0x01000000
+
+/*
+ * CFP period register
+ */
+#define AR5212_CFP_PERIOD 0x8024
+
+/*
+ * Next beacon time register
+ */
+#define AR5212_TIMER0 0x8028
+
+/*
+ * Next DMA beacon alert register
+ */
+#define AR5212_TIMER1 0x802c
+
+/*
+ * Next software beacon alert register
+ */
+#define AR5212_TIMER2 0x8030
+
+/*
+ * Next ATIM window time register
+ */
+#define AR5212_TIMER3 0x8034
+
+/*
+ * CFP duration register
+ */
+#define AR5212_CFP_DUR 0x8038
+
+/*
+ * Receive filter register
+ */
+#define AR5212_RX_FILTER 0x803c
+#define AR5212_RX_FILTER_UNICAST 0x00000001
+#define AR5212_RX_FILTER_MULTICAST 0x00000002
+#define AR5212_RX_FILTER_BROADCAST 0x00000004
+#define AR5212_RX_FILTER_CONTROL 0x00000008
+#define AR5212_RX_FILTER_BEACON 0x00000010
+#define AR5212_RX_FILTER_PROMISC 0x00000020
+#define AR5212_RX_FILTER_XR_POLL 0x00000040
+#define AR5212_RX_FILTER_PROBE_REQ 0x00000080
+
+/*
+ * Multicast filter register (lower 32 bits)
+ */
+#define AR5212_MCAST_FIL0 0x8040
+
+/*
+ * Multicast filter register (higher 16 bits)
+ */
+#define AR5212_MCAST_FIL1 0x8044
+
+/*
+ * PCU control register
+ */
+#define AR5212_DIAG_SW 0x8048
+#define AR5212_DIAG_SW_DIS_WEP_ACK 0x00000001
+#define AR5212_DIAG_SW_DIS_ACK 0x00000002
+#define AR5212_DIAG_SW_DIS_CTS 0x00000004
+#define AR5212_DIAG_SW_DIS_ENC 0x00000008
+#define AR5212_DIAG_SW_DIS_DEC 0x00000010
+#define AR5212_DIAG_SW_DIS_RX 0x00000020
+#define AR5212_DIAG_SW_LOOP_BACK 0x00000040
+#define AR5212_DIAG_SW_CORR_FCS 0x00000080
+#define AR5212_DIAG_SW_CHAN_INFO 0x00000100
+#define AR5212_DIAG_SW_EN_SCRAM_SEED 0x00000200
+#define AR5212_DIAG_SW_ECO_ENABLE 0x00000400
+#define AR5212_DIAG_SW_SCRAM_SEED_M 0x0001fc00
+#define AR5212_DIAG_SW_SCRAM_SEED_S 10
+#define AR5212_DIAG_SW_FRAME_NV0 0x00020000
+#define AR5212_DIAG_SW_OBSPT_M 0x000c0000
+#define AR5212_DIAG_SW_OBSPT_S 18
+
+/*
+ * TSF (clock) register (lower 32 bits)
+ */
+#define AR5212_TSF_L32 0x804c
+
+/*
+ * TSF (clock) register (higher 32 bits)
+ */
+#define AR5212_TSF_U32 0x8050
+
+/*
+ * ADDAC test register
+ */
+#define AR5212_ADDAC_TEST 0x8054
+
+/*
+ * Default antenna register
+ */
+#define AR5212_DEFAULT_ANTENNA 0x8058
+
+/*
+ * Last beacon timestamp register
+ */
+#define AR5212_LAST_TSTP 0x8080
+
+/*
+ * NAV register (current)
+ */
+#define AR5212_NAV 0x8084
+
+/*
+ * RTS success register
+ */
+#define AR5212_RTS_OK 0x8088
+
+/*
+ * RTS failure register
+ */
+#define AR5212_RTS_FAIL 0x808c
+
+/*
+ * ACK failure register
+ */
+#define AR5212_ACK_FAIL 0x8090
+
+/*
+ * FCS failure register
+ */
+#define AR5212_FCS_FAIL 0x8094
+
+/*
+ * Beacon count register
+ */
+#define AR5212_BEACON_CNT 0x8098
+
+/*
+ * XR (eXtended Range) mode register
+ */
+#define AR5212_XRMODE 0x80c0
+#define AR5212_XRMODE_POLL_TYPE_M 0x0000003f
+#define AR5212_XRMODE_POLL_TYPE_S 0
+#define AR5212_XRMODE_POLL_SUBTYPE_M 0x0000003c
+#define AR5212_XRMODE_POLL_SUBTYPE_S 2
+#define AR5212_XRMODE_POLL_WAIT_ALL 0x00000080
+#define AR5212_XRMODE_SIFS_DELAY 0x000fff00
+#define AR5212_XRMODE_FRAME_HOLD_M 0xfff00000
+#define AR5212_XRMODE_FRAME_HOLD_S 20
+
+/*
+ * XR delay register
+ */
+#define AR5212_XRDELAY 0x80c4
+#define AR5212_XRDELAY_SLOT_DELAY_M 0x0000ffff
+#define AR5212_XRDELAY_SLOT_DELAY_S 0
+#define AR5212_XRDELAY_CHIRP_DELAY_M 0xffff0000
+#define AR5212_XRDELAY_CHIRP_DELAY_S 16
+
+/*
+ * XR timeout register
+ */
+#define AR5212_XRTIMEOUT 0x80c8
+#define AR5212_XRTIMEOUT_CHIRP_M 0x0000ffff
+#define AR5212_XRTIMEOUT_CHIRP_S 0
+#define AR5212_XRTIMEOUT_POLL_M 0xffff0000
+#define AR5212_XRTIMEOUT_POLL_S 16
+
+/*
+ * XR chirp register
+ */
+#define AR5212_XRCHIRP 0x80cc
+#define AR5212_XRCHIRP_SEND 0x00000001
+#define AR5212_XRCHIRP_GAP 0xffff0000
+
+/*
+ * XR stomp register
+ */
+#define AR5212_XRSTOMP 0x80d0
+#define AR5212_XRSTOMP_TX 0x00000001
+#define AR5212_XRSTOMP_RX_ABORT 0x00000002
+#define AR5212_XRSTOMP_RSSI_THRES 0x0000ff00
+
+/*
+ * First enhanced sleep register
+ */
+#define AR5212_SLEEP0 0x80d4
+#define AR5212_SLEEP0_NEXT_DTIM_M 0x0007ffff
+#define AR5212_SLEEP0_NEXT_DTIM_S 0
+#define AR5212_SLEEP0_ASSUME_DTIM 0x00080000
+#define AR5212_SLEEP0_ENH_SLEEP_EN 0x00100000
+#define AR5212_SLEEP0_CAPTO_M 0xff000000
+#define AR5212_SLEEP0_CAPTO_S 24
+
+/*
+ * Second enhanced sleep register
+ */
+#define AR5212_SLEEP1 0x80d8
+#define AR5212_SLEEP1_NEXT_TIM_M 0x0007ffff
+#define AR5212_SLEEP1_NEXT_TIM_S 0
+#define AR5212_SLEEP1_BEACON_TO_M 0xff000000
+#define AR5212_SLEEP1_BEACON_TO_S 24
+
+/*
+ * Third enhanced sleep register
+ */
+#define AR5212_SLEEP2 0x80dc
+#define AR5212_SLEEP2_TIM_PER_M 0x0000ffff
+#define AR5212_SLEEP2_TIM_PER_S 0
+#define AR5212_SLEEP2_DTIM_PER_M 0xffff0000
+#define AR5212_SLEEP2_DTIM_PER_S 16
+
+/*
+ * BSSID mask registers
+ */
+#define AR5212_BSS_IDM0 0x80e0
+#define AR5212_BSS_IDM1 0x80e4
+
+/*
+ * TX power control (TPC) register
+ */
+#define AR5212_TXPC 0x80e8
+#define AR5212_TXPC_ACK_M 0x0000003f
+#define AR5212_TXPC_ACK_S 0
+#define AR5212_TXPC_CTS_M 0x00003f00
+#define AR5212_TXPC_CTS_S 8
+#define AR5212_TXPC_CHIRP_M 0x003f0000
+#define AR5212_TXPC_CHIRP_S 22
+
+/*
+ * Profile count registers
+ */
+#define AR5212_PROFCNT_TX 0x80ec
+#define AR5212_PROFCNT_RX 0x80f0
+#define AR5212_PROFCNT_RXCLR 0x80f4
+#define AR5212_PROFCNT_CYCLE 0x80f8
+
+/*
+ * TSF parameter register
+ */
+#define AR5212_TSF_PARM 0x8104
+#define AR5212_TSF_PARM_INC_M 0x000000ff
+#define AR5212_TSF_PARM_INC_S 0
+
+/*
+ * PHY error filter register
+ */
+#define AR5212_PHY_ERR_FIL 0x810c
+#define AR5212_PHY_ERR_FIL_RADAR 0x00000020
+#define AR5212_PHY_ERR_FIL_OFDM 0x00020000
+#define AR5212_PHY_ERR_FIL_CCK 0x02000000
+
+/*
+ * Rate duration register
+ */
+#define AR5212_RATE_DUR_0 0x8700
+#define AR5212_RATE_DUR(_n) (AR5212_RATE_DUR_0 + ((_n) << 2))
+
+/*
+ * Key table (WEP) register
+ */
+#define AR5212_KEYTABLE_0 0x8800
+#define AR5212_KEYTABLE(n) (AR5212_KEYTABLE_0 + ((n) * 32))
+#define AR5212_KEYTABLE_TYPE_40 0x00000000
+#define AR5212_KEYTABLE_TYPE_104 0x00000001
+#define AR5212_KEYTABLE_TYPE_128 0x00000003
+#define AR5212_KEYTABLE_TYPE_TKIP 0x00000004
+#define AR5212_KEYTABLE_TYPE_AES 0x00000005
+#define AR5212_KEYTABLE_TYPE_CCM 0x00000006
+#define AR5212_KEYTABLE_TYPE_NULL 0x00000007
+#define AR5212_KEYTABLE_ANTENNA 0x00000008
+#define AR5212_KEYTABLE_VALID 0x00008000
+
+#define AR5212_KEYTABLE_SIZE 64
+#define AR5212_KEYCACHE_SIZE 8
+
+/*
+ * PHY register
+ */
+#define AR5212_PHY(_n) (0x9800 + ((_n) << 2))
+#define AR5212_PHY_SHIFT_2GHZ 0x00004007
+#define AR5212_PHY_SHIFT_5GHZ 0x00000007
+
+/*
+ * PHY turbo mode register
+ */
+#define AR5212_PHY_TURBO 0x9804
+#define AR5212_PHY_TURBO_MODE 0x00000001
+#define AR5212_PHY_TURBO_SHORT 0x00000002
+
+/*
+ * PHY agility command register
+ */
+#define AR5212_PHY_AGC 0x9808
+#define AR5212_PHY_AGC_DISABLE 0x08000000
+
+/*
+ * PHY timing register
+ */
+#define AR5212_PHY_TIMING_3 0x9814
+#define AR5212_PHY_TIMING_3_DSC_MAN 0xfffe0000
+#define AR5212_PHY_TIMING_3_DSC_MAN_S 17
+#define AR5212_PHY_TIMING_3_DSC_EXP 0x0001e000
+#define AR5212_PHY_TIMING_3_DSC_EXP_S 13
+
+/*
+ * PHY chip revision register
+ */
+#define AR5212_PHY_CHIP_ID 0x9818
+
+/*
+ * PHY activation register
+ */
+#define AR5212_PHY_ACTIVE 0x981c
+#define AR5212_PHY_ENABLE 0x00000001
+#define AR5212_PHY_DISABLE 0x00000002
+
+/*
+ * PHY agility control register
+ */
+#define AR5212_PHY_AGCCTL 0x9860
+#define AR5212_PHY_AGCCTL_CAL 0x00000001
+#define AR5212_PHY_AGCCTL_NF 0x00000002
+
+/*
+ * PHY noise floor status register
+ */
+#define AR5212_PHY_NF 0x9864
+#define AR5212_PHY_NF_M 0x000001ff
+#define AR5212_PHY_NF_ACTIVE 0x00000100
+#define AR5212_PHY_NF_RVAL(_n) (((_n) >> 19) & AR5212_PHY_NF_M)
+#define AR5212_PHY_NF_AVAL(_n) (-((_n) ^ AR5212_PHY_NF_M) + 1)
+#define AR5212_PHY_NF_SVAL(_n) (((_n) & AR5212_PHY_NF_M) | (1 << 9))
+
+/*
+ * PHY sleep registers
+ */
+#define AR5212_PHY_SCR 0x9870
+#define AR5212_PHY_SCR_32MHZ 0x0000001f
+#define AR5212_PHY_SLMT 0x9874
+#define AR5212_PHY_SLMT_32MHZ 0x0000007f
+#define AR5212_PHY_SCAL 0x9878
+#define AR5212_PHY_SCAL_32MHZ 0x0000000e
+
+/*
+ * PHY PLL control register
+ */
+#define AR5212_PHY_PLL 0x987c
+#define AR5212_PHY_PLL_40MHZ 0x000000aa
+#define AR5212_PHY_PLL_44MHZ 0x000000ab
+#define AR5212_PHY_PLL_AR5111 0x00000000
+#define AR5212_PHY_PLL_AR5112 0x00000040
+
+/*
+ * PHY receiver delay register
+ */
+#define AR5212_PHY_RX_DELAY 0x9914
+#define AR5212_PHY_RX_DELAY_M 0x00003fff
+
+/*
+ * PHY timing IQ control register
+ */
+#define AR5212_PHY_IQ 0x9920
+#define AR5212_PHY_IQ_CORR_Q_Q_COFF 0x0000001f
+#define AR5212_PHY_IQ_CORR_Q_I_COFF 0x000007e0
+#define AR5212_PHY_IQ_CORR_Q_I_COFF_S 5
+#define AR5212_PHY_IQ_CORR_ENABLE 0x00000800
+#define AR5212_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000
+#define AR5212_PHY_IQ_CAL_NUM_LOG_MAX_S 12
+#define AR5212_PHY_IQ_RUN 0x00010000
+
+/*
+ * PHY PAPD probe register
+ */
+#define AR5212_PHY_PAPD_PROBE 0x9930
+#define AR5212_PHY_PAPD_PROBE_TXPOWER 0x00007e00
+#define AR5212_PHY_PAPD_PROBE_TXPOWER_S 9
+#define AR5212_PHY_PAPD_PROBE_TX_NEXT 0x00008000
+#define AR5212_PHY_PAPD_PROBE_GAINF 0xfe000000
+#define AR5212_PHY_PAPD_PROBE_GAINF_S 25
+
+/*
+ * PHY TX power registers
+ */
+#define AR5212_PHY_TXPOWER_RATE1 0x9934
+#define AR5212_PHY_TXPOWER_RATE2 0x9938
+#define AR5212_PHY_TXPOWER_RATE_MAX 0x993c
+#define AR5212_PHY_TXPOWER_RATE_MAX_TPC_ENABLE 0x00000040
+#define AR5212_PHY_TXPOWER_RATE3 0xa234
+#define AR5212_PHY_TXPOWER_RATE4 0xa238
+
+/*
+ * PHY frame control register
+ */
+#define AR5212_PHY_FC 0x9944
+#define AR5212_PHY_FC_TX_CLIP 0x00000038
+#define AR5212_PHY_FC_TX_CLIP_S 3
+
+/*
+ * PHY radar detection enable register
+ */
+#define AR5212_PHY_RADAR 0x9954
+#define AR5212_PHY_RADAR_DISABLE 0x00000000
+#define AR5212_PHY_RADAR_ENABLE 0x00000001
+
+/*
+ * PHY antenna switch table registers
+ */
+#define AR5212_PHY_ANT_SWITCH_TABLE_0 0x9960
+#define AR5212_PHY_ANT_SWITCH_TABLE_1 0x9964
+
+/*
+ * PHY clock sleep registers
+ */
+#define AR5212_PHY_SCLOCK 0x99f0
+#define AR5212_PHY_SCLOCK_32MHZ 0x0000000c
+#define AR5212_PHY_SDELAY 0x99f4
+#define AR5212_PHY_SDELAY_32MHZ 0x000000ff
+#define AR5212_PHY_SPENDING 0x99f8
+#define AR5212_PHY_SPENDING_AR5111 0x00000018
+#define AR5212_PHY_SPENDING_AR5112 0x00000014
+
+/*
+ * PHY timing IQ calibration result register
+ */
+#define AR5212_PHY_IQRES_CAL_PWR_I 0x9c10
+#define AR5212_PHY_IQRES_CAL_PWR_Q 0x9c14
+#define AR5212_PHY_IQRES_CAL_CORR 0x9c18
+
+/*
+ * PHY current RSSI register
+ */
+#define AR5212_PHY_CURRENT_RSSI 0x9c1c
+
+/*
+ * PHY PCDAC TX power register
+ */
+#define AR5212_PHY_PCDAC_TXPOWER(_n) (0xa180 + ((_n) << 2))
+
+/*
+ * PHY mode register
+ */
+#define AR5212_PHY_MODE 0x0a200
+#define AR5212_PHY_MODE_MOD 0x00000001
+#define AR5212_PHY_MODE_MOD_OFDM 0
+#define AR5212_PHY_MODE_MOD_CCK 1
+#define AR5212_PHY_MODE_FREQ 0x00000002
+#define AR5212_PHY_MODE_FREQ_5GHZ 0
+#define AR5212_PHY_MODE_FREQ_2GHZ 2
+#define AR5212_PHY_MODE_MOD_DYN 0x00000004
+#define AR5212_PHY_MODE_RAD 0x00000008
+#define AR5212_PHY_MODE_RAD_AR5111 0
+#define AR5212_PHY_MODE_RAD_AR5112 8
+#define AR5212_PHY_MODE_XR 0x00000010
+
+/*
+ * PHY 2GHz gain register
+ */
+#define AR5212_PHY_GAIN_2GHZ 0xa20c
+#define AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000
+#define AR5212_PHY_GAIN_2GHZ_MARGIN_TXRX_S 18
+
+#endif
+
+/*
+ * Common ar5xxx EEPROM data registers
+ */
+
+#define EEPROM_MAGIC 0x003d
+#define EEPROM_MAGIC_VALUE 0x5aa5
+#define EEPROM_PROTECT 0x003f
+#define EEPROM_PROTECT_RD_0_31 0x0001
+#define EEPROM_PROTECT_WR_0_31 0x0002
+#define EEPROM_PROTECT_RD_32_63 0x0004
+#define EEPROM_PROTECT_WR_32_63 0x0008
+#define EEPROM_PROTECT_RD_64_127 0x0010
+#define EEPROM_PROTECT_WR_64_127 0x0020
+#define EEPROM_PROTECT_RD_128_191 0x0040
+#define EEPROM_PROTECT_WR_128_191 0x0080
+#define EEPROM_PROTECT_RD_192_207 0x0100
+#define EEPROM_PROTECT_WR_192_207 0x0200
+#define EEPROM_PROTECT_RD_208_223 0x0400
+#define EEPROM_PROTECT_WR_208_223 0x0800
+#define EEPROM_PROTECT_RD_224_239 0x1000
+#define EEPROM_PROTECT_WR_224_239 0x2000
+#define EEPROM_PROTECT_RD_240_255 0x4000
+#define EEPROM_PROTECT_WR_240_255 0x8000
+#define EEPROM_REG_DOMAIN 0x00bf
+#define EEPROM_INFO_BASE 0x00c0
+#define EEPROM_INFO_MAX \
+ (0x400 - EEPROM_INFO_BASE)
+#define EEPROM_INFO(_n) (EEPROM_INFO_BASE + (_n))
+
+#define EEPROM_VERSION EEPROM_INFO(1)
+#define EEPROM_VERSION_3_0 0x3000
+#define EEPROM_VERSION_3_1 0x3001
+#define EEPROM_VERSION_3_2 0x3002
+#define EEPROM_VERSION_3_3 0x3003
+#define EEPROM_VERSION_3_4 0x3004
+#define EEPROM_VERSION_4_0 0x4000
+#define EEPROM_VERSION_4_1 0x4001
+#define EEPROM_VERSION_4_2 0x4002
+#define EEPROM_VERSION_4_3 0x4003
+#define EEPROM_VERSION_4_6 0x4006
+#define EEPROM_VERSION_4_7 0x3007
+
+#define EEPROM_MODE_11A 0
+#define EEPROM_MODE_11B 1
+#define EEPROM_MODE_11G 2
+
+#define EEPROM_HDR EEPROM_INFO(2)
+#define EEPROM_HDR_11A(_v) (((_v) >> EEPROM_MODE_11A) & 0x1)
+#define EEPROM_HDR_11B(_v) (((_v) >> EEPROM_MODE_11B) & 0x1)
+#define EEPROM_HDR_11G(_v) (((_v) >> EEPROM_MODE_11G) & 0x1)
+#define EEPROM_HDR_T_2GHZ_DIS(_v) (((_v) >> 3) & 0x1)
+#define EEPROM_HDR_T_5GHZ_DBM(_v) (((_v) >> 4) & 0x7f)
+#define EEPROM_HDR_DEVICE(_v) (((_v) >> 11) & 0x7)
+#define EEPROM_HDR_T_5GHZ_DIS(_v) (((_v) >> 15) & 0x1)
+#define EEPROM_HDR_RFKILL(_v) (((_v) >> 14) & 0x1)
+
+#define EEPROM_RFKILL_GPIO_SEL 0x0000001c
+#define EEPROM_RFKILL_GPIO_SEL_S 2
+#define EEPROM_RFKILL_POLARITY 0x00000002
+#define EEPROM_RFKILL_POLARITY_S 1
+
+/* Newer EEPROMs are using a different offset */
+#define EEPROM_OFF(_v, _v3_0, _v3_3) \
+ (((_v) >= EEPROM_VERSION_3_3) ? _v3_3 : _v3_0)
+
+#define EEPROM_ANT_GAIN(_v) EEPROM_OFF(_v, 0x00c4, 0x00c3)
+#define EEPROM_ANT_GAIN_5GHZ(_v) ((int8_t)(((_v) >> 8) & 0xff))
+#define EEPROM_ANT_GAIN_2GHZ(_v) ((int8_t)((_v) & 0xff))
+
+#define EEPROM_MODES_11A(_v) EEPROM_OFF(_v, 0x00c5, 0x00d4)
+#define EEPROM_MODES_11B(_v) EEPROM_OFF(_v, 0x00d0, 0x00f2)
+#define EEPROM_MODES_11G(_v) EEPROM_OFF(_v, 0x00da, 0x010d)
+#define EEPROM_CTL(_v) EEPROM_OFF(_v, 0x00e4, 0x0128)
+
+/* Since 3.1 */
+#define EEPROM_OBDB0_2GHZ 0x00ec
+#define EEPROM_OBDB1_2GHZ 0x00ed
+
+/* Misc values available since EEPROM 4.0 */
+#define EEPROM_MISC0 0x00c4
+#define EEPROM_EARSTART(_v) ((_v) & 0xfff)
+#define EEPROM_EEMAP(_v) (((_v) >> 14) & 0x3)
+#define EEPROM_MISC1 0x00c5
+#define EEPROM_TARGET_PWRSTART(_v) ((_v) & 0xfff)
+#define EEPROM_HAS32KHZCRYSTAL(_v) (((_v) >> 14) & 0x1)
+
+/* Some EEPROM defines */
+#define EEPROM_EEP_SCALE 100
+#define EEPROM_EEP_DELTA 10
+#define EEPROM_MODES 3
+#define EEPROM_5GHZ_CHAN 10
+#define EEPROM_2GHZ_CHAN 3
+#define EEPROM_MAX_CHAN 10
+#define EEPROM_PCDAC 11
+#define EEPROM_TEST_FREQ 8
+#define EEPROM_EDGES 8
+#define EEPROM_INTERCEPTS 11
+#define EEPROM_FREQ_M(_v) EEPROM_OFF(_v, 0x7f, 0xff)
+#define EEPROM_PCDAC_M 0x3f
+#define EEPROM_PCDAC_START 1
+#define EEPROM_PCDAC_STOP 63
+#define EEPROM_PCDAC_STEP 1
+#define EEPROM_NON_EDGE_M 0x40
+#define EEPROM_CHANNEL_POWER 8
+#define EEPROM_OBDB 4
+#define EEPROM_OBDB_DIS 0xffff
+#define EEPROM_CHANNEL_DIS 0xff
+#define EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
+#define EEPROM_CTLS(_v) _EEPROM_OFF(_v, 16, 32)
+#define EEPROM_MAX_CTLS 32
+#define EEPROM_XPD_PER_CHANNEL 4
+#define EEPROM_XPD0_POINTS 4
+#define EEPROM_XPD3_POINTS 3
+#define EEPROM_INTERCEPT_10_2GHZ 35
+#define EEPROM_INTERCEPT_10_5GHZ 55
+#define EEPROM_POWER_M 0x3f
+#define EEPROM_POWER_MIN 0
+#define EEPROM_POWER_MAX 3150
+#define EEPROM_POWER_STEP 50
+#define EEPROM_POWER_TABLE_SIZE 64
+#define EEPROM_POWER_LOC_11B 4
+#define EEPROM_POWER_LOC_11G 6
+#define EEPROM_I_GAIN 10
+#define EEPROM_CCK_OFDM_DELTA 15
+#define EEPROM_IQ_CAL 2
+
+
+#define TXDESC_VEOL 0x20

awk isnum function

function isnum(n) {return n ~ /^[+-]?[0-9]+$/}

how about

function isnum(n) { return n ~ /^[+-]?[0-9]+\.?[0-9]*$/ }

pipe in linux (from somewhere in the internet...)

Pipes are commonly used for interprocess communication. But the major disadvantage of pipes is that they can be used only by one process (there are readers and writers within the same process) or the processes which share the same file descriptor table (normally the processes and the child processes or threads created by them). Thus pipes have this big limitation: they cannot pass information between unrelated processes. This is because they do not share the same file descriptor table. But if names are given to the pipes, then one would be able to read or write data to them just like a normal file. The processes need not even share anything with each otherFIFO (First In First Out) are also called named pipes. The main features of FIFO are
1. It implements FIFO feature of the pipes
2. They can be opened just like normal files using their names
3. Data can be read from or written to the fifo

Working with FIFO in a Shell
Creating a FIFO

mkfifo

creates fifo- the named pipes

Syntax

mkfifo [options] fifo_name

Example

$ mkfifo fifo

There is one more way by which we can FIFO using mknod. mknod is used to create block or character special files.

$ mknod [OPTION]... NAME TYPE

To create a FIFO fifo1

$ mknod fifo1 p

where p coressponds to file type : pipe (remember FIFO is a named pipe).

Reading/ Writing data from/to a FIFO
Let’s open two terminals
In the first terminal

$ cat > fifo

we are experimenting with the FIFOThis is second line. After opening the fifo in the second terminal for readingusing cat, you will notice the above two lines displayed there.
Now open the second terminal and go to the directory containing the FIFO ‘fifo’

$ cat fifo

we are experimenting with the FIFOThis is second line. After opening the fifo in the second terminal for reading
Now keep on writing to the first terminal. You will notice that every time you press enter, the coressponding line appears in the second terminal.

Pressing CTRL+D in the first terminal terminates writing to the fifo. This also terminates the second process because reading from the fifo now generates a “BROKEN PIPE” signal. The default action for this is to terminate the process.

Let us now see the details of the file ‘fifo’

$ ls -l fifo
prw-r--r-- 1 user user 0 Feb 14 10:05 fifo

The p in the beginning denotes that it is a pipe.

Let’s see more details about the pipe using stat

$ stat fifo
File: `fifo'Size: 0 Blocks: 0 IO Block: 4096 fifo
Device: fd00h/64768d Inode: 1145493 Links: 1
Access: (0644/prw-r--r--) Uid: ( 0/ user) Gid: ( 0/ user)
Access: 2008-02-14 10:05:49.000000000 +0530
Modify: 2008-02-14 10:05:49.000000000 +0530
Change: 2008-02-14 10:05:49.000000000 +0530

If you notice carefully, FIFOs just like a normal file possess all the details like inode number, the number of links to it, the access, modification times, size and the access permissions.

As in the case of pipes, there can be multiple readers and writers to a pipe. Try opening multiple terminals to read from and write to a pipe.

For more updates, check Programming Insights.

madwifi patches

1. add in-kernel-network-monitoring
2. add "report buffer full" from ieee80211_output to network kernel
3. buffer size control
4. 802.11e enabled with adhoc mode
5. worse than useless ttl-based packet filtering (beyond crap) who would use this?

the following

diff -Nru madwifi-original/ath/if_ath.c madwifi-new/ath/if_ath.c
--- madwifi-original/ath/if_ath.c 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/ath/if_ath.c 2009-10-15 12:38:40.000000000 +0200
@@ -467,6 +467,8 @@
MODULE_PARM_DESC(ratectl, "Rate control algorithm [amrr|minstrel|onoe|sample], "
"defaults to '" DEF_RATE_CTL "'");

+static int iknm_portnum=30010;
+
#ifdef AR_DEBUG
static int ath_debug = 0;
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,52))
@@ -563,6 +565,213 @@
return f;
}

+/* jyyoo (jaeyong): in-kernel-network-monitoring */
+int thread_deliver_ath_hardstart(void* data)
+{
+ struct ath_softc* sc = (struct ath_softc*)data;
+
+ init_waitqueue_head(&sc->sc_queue_send);
+
+ sc->sc_kthread_send_alive = 1;
+ while( sc->sc_kthread_send_alive )
+ {
+ int ret;
+ int h, t;
+ int total_info;
+ int total_packet;
+ int debug_cnt=0;
+
+ mm_segment_t oldmm;
+
+ h = sc->sc_monitor_head;
+ t = sc->sc_monitor_tail;
+
+ if( h < t ) h += MAX_MPARAM;
+
+ total_info = h-t;
+
+ total_packet = total_info / MAX_MPARAM_PERPACKET;
+ if( total_info % MAX_MPARAM_PERPACKET ) total_packet += 1;
+
+ while( h != t )
+ {
+ debug_cnt ++;
+ if( debug_cnt > 30 ) {
+ printk("critical loop detected!!!\n");
+ break;
+ }
+ /* first determine iov_base */
+ sc->sc_iov_msg.iov_base = (char*)&sc->sc_monitor_param[t];
+
+ /* and then determine iov_len */
+ if( sc->sc_monitor_head > sc->sc_monitor_tail )
+ {
+ if( (h - t) > MAX_MPARAM_PERPACKET )
+ {
+ sc->sc_iov_msg.iov_len = MAX_MPARAM_PERPACKET * sizeof(struct monitor_param);
+ t+=MAX_MPARAM_PERPACKET;
+ }
+ else
+ {
+ sc->sc_iov_msg.iov_len = (h-t)*sizeof(struct monitor_param);
+ t = h;
+ }
+ }
+ else
+ {
+ int pre_t=t;
+ if( (h - t) > MAX_MPARAM_PERPACKET )
+ {
+ pre_t+=MAX_MPARAM_PERPACKET;
+ }
+ else
+ {
+ pre_t = h;
+ }
+
+ if( pre_t >= MAX_MPARAM )
+ {
+ sc->sc_iov_msg.iov_len = (MAX_MPARAM - t) * sizeof(struct monitor_param);
+ t = 0;
+ h -= MAX_MPARAM;
+ }
+ else
+ {
+ if( (h - t) > MAX_MPARAM_PERPACKET )
+ {
+ sc->sc_iov_msg.iov_len = MAX_MPARAM_PERPACKET * sizeof(struct monitor_param);
+ t+=MAX_MPARAM_PERPACKET;
+ }
+ else
+ {
+ sc->sc_iov_msg.iov_len = (h-t)*sizeof(struct monitor_param);
+ t = h;
+ }
+
+ }
+ }
+
+ oldmm = get_fs();
+ set_fs(KERNEL_DS);
+ if( (ret = sock_sendmsg( sc->sc_sock_mclient, &sc->sc_msghdr, sc->sc_iov_msg.iov_len )) < 0 )
+ {
+ printk("IKNM: send error: %d\n", ret);
+ }
+ set_fs(oldmm);
+ }
+ sc->sc_monitor_tail = h;
+ if( sc->sc_iknm_enable )
+ interruptible_sleep_on_timeout(&sc->sc_queue_send, HZ/20);
+ else
+ interruptible_sleep_on_timeout(&sc->sc_queue_send, HZ);
+ }
+ complete_and_exit(NULL, 0);
+ return 0;
+}
+/* jyyoo (jaeyong): in-kernel-network-monitoring */
+int thread_deliver_rx_tasklet(void* data)
+{
+ struct ath_softc* sc = (struct ath_softc*)data;
+
+ init_waitqueue_head(&sc->sc_recv_queue_send);
+
+ sc->sc_recv_kthread_send_alive = 1;
+ while( sc->sc_recv_kthread_send_alive )
+ {
+ int ret;
+ int h, t;
+ int total_info;
+ int total_packet;
+ int debug_cnt=0;
+
+ mm_segment_t oldmm;
+
+ h = sc->sc_recv_monitor_head;
+ t = sc->sc_recv_monitor_tail;
+
+ if( h < t ) h += MAX_MPARAM;
+
+ total_info = h-t;
+
+ total_packet = total_info / MAX_MPARAM_PERPACKET;
+ if( total_info % MAX_MPARAM_PERPACKET ) total_packet += 1;
+
+ while( h != t )
+ {
+ debug_cnt ++;
+ if( debug_cnt > 30 ) {
+ printk("critical loop detected!!!\n");
+ break;
+ }
+ /* first determine iov_base */
+ sc->sc_recv_iov_msg.iov_base = (char*)&sc->sc_recv_monitor_param[t];
+
+ /* and then determine iov_len */
+ if( sc->sc_recv_monitor_head > sc->sc_recv_monitor_tail )
+ {
+ if( (h - t) > MAX_MPARAM_PERPACKET )
+ {
+ sc->sc_recv_iov_msg.iov_len = MAX_MPARAM_PERPACKET * sizeof(struct monitor_param_recv);
+
+ t+=MAX_MPARAM_PERPACKET;
+ }
+ else
+ {
+ sc->sc_recv_iov_msg.iov_len = (h-t)*sizeof(struct monitor_param_recv);
+ t = h;
+ }
+ }
+ else
+ {
+ int pre_t=t;
+ if( (h - t) > MAX_MPARAM_PERPACKET )
+ {
+ pre_t+=MAX_MPARAM_PERPACKET;
+ }
+ else
+ {
+ pre_t = h;
+ }
+
+ if( pre_t >= MAX_MPARAM )
+ {
+ sc->sc_recv_iov_msg.iov_len = (MAX_MPARAM - t) * sizeof(struct monitor_param_recv);
+ t = 0;
+ h -= MAX_MPARAM;
+ }
+ else
+ {
+ if( (h - t) > MAX_MPARAM_PERPACKET )
+ {
+ sc->sc_recv_iov_msg.iov_len = MAX_MPARAM_PERPACKET * sizeof(struct monitor_param_recv);
+ t+=MAX_MPARAM_PERPACKET;
+ }
+ else
+ {
+ sc->sc_recv_iov_msg.iov_len = (h-t)*sizeof(struct monitor_param_recv);
+ t = h;
+ }
+ }
+ }
+ oldmm = get_fs();
+ set_fs(KERNEL_DS);
+ if( (ret = sock_sendmsg( sc->sc_recv_sock_mclient, &sc->sc_recv_msghdr, sc->sc_recv_iov_msg.iov_len )) < 0 )
+ {
+ printk("IKNM: send error: %d\n", ret);
+ }
+ set_fs(oldmm);
+ }
+ sc->sc_recv_monitor_tail = h;
+ if( sc->sc_iknm_enable )
+ interruptible_sleep_on_timeout(&sc->sc_recv_queue_send, HZ/2);
+ else
+ interruptible_sleep_on_timeout(&sc->sc_recv_queue_send, HZ);
+ }
+ complete_and_exit(NULL, 0);
+ return 0;
+}
+
+
/* Initialize ath_softc structure */

int
@@ -587,6 +796,10 @@

sc->sc_hwinfo = &generic_hw_info;

+ /* jyyoo add marker */
+ printk("jyyoo marker v.0.1.2\n");
+ ic->ic_enable_ttl_pf = 0;
+ ic->ic_adhoc_edca = 0;
/* Allocate space for dynamically determined maximum VAP count */
sc->sc_bslot =
kmalloc(ath_maxvaps * sizeof(struct ieee80211vap*), GFP_KERNEL);
@@ -1187,6 +1400,168 @@
sc->sc_noise_immunity = -1;
sc->sc_ofdm_weak_det = -1;

+ /* jyyoo (jaeyong): in-kernel-network-monitoring */
+
+ sc->sc_iknm_enable = 1;
+
+ /* just for the heads up */
+ printk("sizeof(struct timeval)=%d\n", sizeof(struct timeval));
+
+ /* default port number: 30001 */
+ sc->sc_port_number = 30001;
+ sc->sc_serv_addr.sin_family = AF_INET;
+ /* default monitor server ip address: 172.17.255.254 (panther) */
+ sc->sc_serv_addr.sin_addr.s_addr = (in_aton("172.17.255.254"));
+ sc->sc_serv_addr.sin_port = htons(sc->sc_port_number);
+
+ sc->sc_serv_addr2.sin_family = AF_INET;
+ sc->sc_serv_addr2.sin_addr.s_addr = htonl(INADDR_ANY);
+ sc->sc_serv_addr2.sin_port = htons(iknm_portnum++);
+ spin_lock_init(&sc->sc_send_lock);
+ sc->sc_monitor_head = 0;
+ sc->sc_monitor_tail = 0;
+ sc->dp_exchange_buffer_drop = 0;
+
+ if( sock_create(AF_INET, SOCK_DGRAM, 0, &sc->sc_sock_mclient) < 0 )
+ {
+ printk("IKNM: Error creating socket\n");
+ sc->sc_sock_mclient = NULL;
+ }
+ else
+ {
+
+ int i;
+ int ret;
+ mm_segment_t oldmm;
+
+ if( sc->sc_sock_mclient->ops->bind( sc->sc_sock_mclient,
+ (struct sockaddr*)&sc->sc_serv_addr2,
+ sizeof(sc->sc_serv_addr2) ) < 0 )
+ {
+ printk("IKNM: Error bind failed\n");
+
+ }
+ else
+ {
+
+ printk("IKNM: socket initiation succeeded; port %d addr: 172.17.255.254\n", sc->sc_port_number);
+
+ for( i=0; i<1024; i++ )
+ sc->sc_msgbuf[i] = i;
+
+
+ sc->sc_msghdr.msg_name = (struct sockaddr*)&sc->sc_serv_addr;
+ sc->sc_msghdr.msg_namelen = sizeof(sc->sc_serv_addr);
+ sc->sc_msghdr.msg_iov = &sc->sc_iov_msg;
+ sc->sc_msghdr.msg_iovlen = 1;
+ sc->sc_msghdr.msg_control = NULL;
+ sc->sc_msghdr.msg_controllen = 0;
+ sc->sc_msghdr.msg_flags = 0;
+
+ sc->sc_iov_msg.iov_base = sc->sc_msgbuf;
+ sc->sc_iov_msg.iov_len = 1024;
+
+ oldmm = get_fs();
+ set_fs(KERNEL_DS);
+
+
+ if( (ret = sock_sendmsg( sc->sc_sock_mclient, &sc->sc_msghdr, sc->sc_iov_msg.iov_len )) < 0 )
+ {
+ printk("IKNM: first send error: %d\n", ret);
+ }
+ else
+ {
+ printk("IKNM: first send succeeded %d\n", ret);
+ }
+
+ set_fs(oldmm);
+ }
+
+ }
+
+ sc->sc_kthread_send_alive = 0;
+
+ sc->sc_kthread_send = kthread_create( thread_deliver_ath_hardstart, sc, "iknm_MAC_monitor" );
+ wake_up_process(sc->sc_kthread_send);
+
+ /* default port number: 30001 */
+ sc->sc_recv_port_number = 30003;
+ sc->sc_recv_serv_addr.sin_family = AF_INET;
+ /* default monitor server ip address: 172.17.255.254 (panther) */
+ sc->sc_recv_serv_addr.sin_addr.s_addr = (in_aton("172.17.255.254"));
+ sc->sc_recv_serv_addr.sin_port = htons(sc->sc_recv_port_number);
+
+ sc->sc_recv_serv_addr2.sin_family = AF_INET;
+ sc->sc_recv_serv_addr2.sin_addr.s_addr = htonl(INADDR_ANY);
+ sc->sc_recv_serv_addr2.sin_port = htons(iknm_portnum++);
+ spin_lock_init(&sc->sc_recv_send_lock);
+ sc->sc_recv_monitor_head = 0;
+ sc->sc_recv_monitor_tail = 0;
+ sc->dp_exchange_buffer_drop = 0;
+
+ if( sock_create(AF_INET, SOCK_DGRAM, 0, &sc->sc_recv_sock_mclient) < 0 )
+ {
+ printk("IKNM: Error creating socket\n");
+ sc->sc_recv_sock_mclient = NULL;
+ }
+ else
+ {
+
+ int i;
+ int ret;
+ mm_segment_t oldmm;
+
+ if( sc->sc_recv_sock_mclient->ops->bind( sc->sc_recv_sock_mclient,
+ (struct sockaddr*)&sc->sc_recv_serv_addr2,
+ sizeof(sc->sc_recv_serv_addr2) ) < 0 )
+ {
+ printk("IKNM: Error bind failed\n");
+
+ }
+ else
+ {
+
+ printk("IKNM: socket initiation succeeded; port %d addr: 172.17.255.254 (monitor_param size:%d)\n", sc->sc_recv_port_number, sizeof(struct monitor_param_recv));
+
+ for( i=0; i<1024; i++ )
+ sc->sc_recv_msgbuf[i] = i;
+ sc->sc_recv_msghdr.msg_name = (struct sockaddr*)&sc->sc_recv_serv_addr;
+ sc->sc_recv_msghdr.msg_namelen = sizeof(sc->sc_recv_serv_addr);
+ sc->sc_recv_msghdr.msg_iov = &sc->sc_recv_iov_msg;
+ sc->sc_recv_msghdr.msg_iovlen = 1;
+ sc->sc_recv_msghdr.msg_control = NULL;
+ sc->sc_recv_msghdr.msg_controllen = 0;
+ sc->sc_recv_msghdr.msg_flags = 0;
+
+ sc->sc_recv_iov_msg.iov_base = sc->sc_recv_msgbuf;
+ sc->sc_recv_iov_msg.iov_len = 1024;
+
+ oldmm = get_fs();
+ set_fs(KERNEL_DS);
+
+
+ if( (ret = sock_sendmsg( sc->sc_recv_sock_mclient, &sc->sc_recv_msghdr, sc->sc_recv_iov_msg.iov_len )) < 0 )
+ {
+ printk("IKNM: first send error: %d\n", ret);
+ }
+ else
+ {
+ printk("IKNM: first send succeeded %d\n", ret);
+ }
+
+ set_fs(oldmm);
+ }
+
+ }
+
+ sc->sc_recv_kthread_send_alive = 0;
+
+ sc->sc_recv_kthread_send = kthread_create( thread_deliver_rx_tasklet, sc, "recv-iknm_MAC_monitor" );
+ wake_up_process(sc->sc_recv_kthread_send);
+
+
+ sc->sc_queue_len = TAIL_DROP_COUNT;
+
return 0;
bad3:
ieee80211_ifdetach(ic);
@@ -3507,6 +3882,9 @@
STAILQ_INIT(&bf_head);

if (SKB_CB(skb)->flags & M_RAW) {
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ sc->sc_stats.ast_jyd_ath_hardstart_raw ++;
+#endif
bf = ath_take_txbuf(sc);
if (bf == NULL) {
/* All DMA buffers full, safe to try again. */
@@ -3543,9 +3921,12 @@
ATH_FF_MAGIC_CLR(skb);
an = ATH_NODE(ni);

+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ sc->sc_stats.ast_jyd_ath_hardstart ++;
+#endif
txq = sc->sc_ac2q[skb->priority];

- if (txq->axq_depth > TAIL_DROP_COUNT) {
+ if (txq->axq_depth > sc->sc_queue_len) {
/* Wish to reserve some DMA buffers, try again later. */
requeue = 1;
goto hardstart_fail;
@@ -3765,9 +4146,15 @@
netif_stop_queue(dev);
sc->sc_devstopped = 1;
/* Stop tracking again we are giving it back*/
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ sc->sc_stats.ast_jyd_ath_hardstart_drop ++;
+#endif
ieee80211_skb_untrack(skb);
return NETDEV_TX_BUSY;
}
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ sc->sc_stats.ast_jyd_ath_hardstart_silent_drop ++;
+#endif
/* Now free the SKBs */
ieee80211_dev_kfree_skb_list(&skb);
return NETDEV_TX_OK;
@@ -6973,6 +7360,47 @@
}
}

+ /* jyyoo (jaeyong): in-kernel-network-monitor */
+ /* information to put:
+ 1. interface queue occupation length
+ 2. retransmission count
+ 3. receiving error count
+ */
+ if( sc->sc_iknm_enable ) {
+ int next_head;
+ sk_buff_data_t network_header = skb->data + 24 /* sizeof wifi header */ + 8 /* sizeof llc */;
+ if( (*(unsigned char*)(network_header)) == 69 ) // it means IP header with header length 20
+ {
+ sc->dp_exchange_buffer_drop ++;
+ next_head = sc->sc_recv_monitor_head + 1;
+ if( next_head >= MAX_MPARAM ) next_head = next_head - MAX_MPARAM;
+
+ if( next_head == sc->sc_recv_monitor_tail ) // exchange buffer is full, just drop this packet
+ {
+ printk("monitoring packet dropped :%d\n", sc->dp_exchange_buffer_drop);
+ }
+ else // insert into the exchange buffer
+ {
+ int h = sc->sc_recv_monitor_head;
+ struct timeval tv;
+ do_gettimeofday(&tv);
+ sc->sc_recv_monitor_param[h].sec = tv.tv_sec;
+ sc->sc_recv_monitor_param[h].msec = tv.tv_usec;
+ memcpy( sc->sc_recv_monitor_param[h].header, skb->data, HEADER_LEN ); // 14 bytes for ethernet header
+ sc->sc_recv_monitor_head = next_head;
+ }
+
+ {
+ int h,t;
+ h = sc->sc_recv_monitor_head;
+ t = sc->sc_recv_monitor_tail;
+ if( h < t ) h += MAX_MPARAM;
+ if( (h-t) > MAX_MPARAM_PERPACKET && sc->sc_recv_kthread_send_alive )
+ wake_up_interruptible(&sc->sc_recv_queue_send);
+ }
+ }
+ }
+
/*
* Locate the node for sender, track state, and then
* pass the (referenced) node up to the 802.11 layer
@@ -8382,6 +8810,58 @@
try0, keyix, antenna, flags, ctsrate, ctsduration, icvlen, ivlen,
comp);

+ /* jyyoo (jaeyong): in-kernel-network-monitor */
+ /* information to put:
+ 1. interface queue occupation length
+ 2. retransmission count
+ 3. receiving error count
+ */
+ if( sc->sc_iknm_enable ) {
+ int next_head;
+
+ /* first check exchange buffe is full or not */
+ next_head = sc->sc_monitor_head + 1;
+ if( next_head >= MAX_MPARAM ) next_head = next_head - MAX_MPARAM;
+
+ if( next_head == sc->sc_monitor_tail ) // exchange buffer is full, just drop this packet
+ {
+ printk("IKNM: exchange buffer is full,,, packet dropped\n");
+ sc->dp_exchange_buffer_drop ++;
+ }
+ else // insert into the exchange buffer
+ {
+ int h = sc->sc_monitor_head;
+ struct timeval tv;
+ do_gettimeofday(&tv);
+ sc->sc_monitor_param[h].sec = tv.tv_sec;
+ sc->sc_monitor_param[h].msec = tv.tv_usec;
+ /* monitor 4 priority queues */
+ sc->sc_monitor_param[h].qlen[WME_AC_VO] = (u_int8_t)(sc->sc_ac2q[WME_AC_VO]->axq_depth);
+ sc->sc_monitor_param[h].qlen[WME_AC_VI] = (u_int8_t)(sc->sc_ac2q[WME_AC_VI]->axq_depth);
+ sc->sc_monitor_param[h].qlen[WME_AC_BE] = (u_int8_t)(sc->sc_ac2q[WME_AC_BE]->axq_depth);
+ sc->sc_monitor_param[h].qlen[WME_AC_BK] = (u_int8_t)(sc->sc_ac2q[WME_AC_BK]->axq_depth);
+ sc->sc_monitor_param[h].ret = (u_int8_t)sc->sc_stats.ast_tx_longretry + sc->sc_stats.ast_tx_shortretry;
+ sc->sc_monitor_param[h].err = (u_int8_t)sc->sc_stats.ast_rx_phyerr;
+ sc->sc_monitor_param[h].modRate = (u_int8_t)txrate;
+ if( skb->network_header )
+ memcpy( sc->sc_monitor_param[h].header, skb->data, HEADER_LEN ); // 14 bytes for ethernet header
+
+
+ sc->sc_monitor_head = next_head;
+ }
+
+ /* if the buffer is quite large, wake up the sending process */
+
+ {
+ int h,t;
+ h = sc->sc_monitor_head;
+ t = sc->sc_monitor_tail;
+ if( h < t ) h += MAX_MPARAM;
+ if( (h-t) > MAX_MPARAM_PERPACKET && sc->sc_kthread_send_alive )
+ wake_up_interruptible(&sc->sc_queue_send);
+ }
+ }
+
/*
* Formulate first tx descriptor with tx controls.
*/
@@ -10886,6 +11366,137 @@

ATH_LOCK(sc);
switch (cmd) {
+
+ /* jyyoo add to enable TTL-based packet filtering */
+ /* it is a part of work around solution for click output packet filtering */
+ case SIOCGTTLPACKETFILTER:
+ {
+ if( copy_to_user(ifr->ifr_data, &ic->ic_enable_ttl_pf, sizeof(ic->ic_enable_ttl_pf)))
+ {
+ printk("madwifi: siocgttlpacketfilter failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ printk("read ttl packet filter : %d\n", ic->ic_enable_ttl_pf);
+ error = 0;
+ }
+ }
+ break;
+ case SIOCSTTLPACKETFILTER:
+ {
+ unsigned char buf [4];
+ if( copy_from_user( buf, ifr->ifr_data, sizeof(buf)))
+ {
+ printk("madwifi: siocsttlpacketfilter failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ ic->ic_enable_ttl_pf = *((u_int32_t*)buf);
+ printk("set ttl packet filter : %d\n", ic->ic_enable_ttl_pf);
+ error = 0;
+ }
+ }
+ break;
+ /* jyyoo finish */
+
+ /* jyyoo add to enable adhoc edca */
+ case SIOCGADHOCEDCA:
+ {
+ if( copy_to_user(ifr->ifr_data, &ic->ic_adhoc_edca, sizeof(ic->ic_adhoc_edca)))
+ {
+ printk("madwifi: siocgadhocedca failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ printk("read adhoc edca : %d\n", ic->ic_adhoc_edca);
+ error = 0;
+ }
+ }
+ break;
+ case SIOCSADHOCEDCA:
+ {
+ unsigned char buf [4];
+ if( copy_from_user( buf, ifr->ifr_data, sizeof(buf)))
+ {
+ printk("madwifi: siocsadhocedca failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ ic->ic_adhoc_edca = *((u_int32_t*)buf);
+ printk("set adhoc edca : %d\n", ic->ic_adhoc_edca);
+ error = 0;
+ }
+ }
+ break;
+ /* jyyoo finish */
+ /* jyyoo (jaeyong) control iknm enable disable */
+ case SIOCGATHIKNM:
+ {
+ if( copy_to_user(ifr->ifr_data, &sc->sc_iknm_enable, sizeof(sc->sc_iknm_enable)))
+ {
+ printk("madwifi: siocathiknm failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ printk("madwifi: siocathiknm succeed : %d\n", sc->sc_iknm_enable);
+ error = 0;
+ }
+ }
+ break;
+ case SIOCSATHIKNM:
+ {
+ unsigned char buf[4];
+ if( copy_from_user( buf, ifr->ifr_data, sizeof(buf)))
+ {
+ printk("madwifi: siocsathiknm failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ sc->sc_iknm_enable = *((int*)buf);
+ printk("set iknm enable: %d\n", sc->sc_iknm_enable );
+ error = 0;
+ }
+ }
+ break;
+ /* jyyoo (jaeyong) control tx queue len */
+ case SIOCGATHBUFLEN:
+ {
+ if( copy_to_user(ifr->ifr_data, &sc->sc_queue_len, sizeof(sc->sc_queue_len)))
+ {
+ printk("madwifi: siocgathbuflen failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ printk("read athbuflen : %d\n", sc->sc_queue_len);
+ error = 0;
+ }
+ }
+ break;
+ case SIOCSATHBUFLEN:
+ {
+ unsigned char buf [4];
+ if( copy_from_user( buf, ifr->ifr_data, sizeof(buf)))
+ {
+ printk("madwifi: siocsathbuflen failed\n");
+ error = -EFAULT;
+ }
+ else
+ {
+ sc->sc_queue_len = *((int*)buf);
+ printk("set athbuflen : %d\n", sc->sc_queue_len);
+ error = 0;
+ }
+ }
+ break;
+
+
case SIOCGATHSTATS:
sc->sc_stats.ast_tx_packets = sc->sc_devstats.tx_packets;
sc->sc_stats.ast_rx_packets = sc->sc_devstats.rx_packets;
diff -Nru madwifi-original/ath/if_athioctl.h madwifi-new/ath/if_athioctl.h
--- madwifi-original/ath/if_athioctl.h 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/ath/if_athioctl.h 2009-10-15 12:37:56.000000000 +0200
@@ -42,6 +42,8 @@
#ifndef _DEV_ATH_ATHIOCTL_H
#define _DEV_ATH_ATHIOCTL_H

+#define JYD_FUNCTION_CALL_FREQUENCY
+
struct ath_stats {
u_int32_t ast_watchdog; /* device reset by watchdog */
u_int32_t ast_hardware; /* fatal hardware error interrupts */
@@ -98,6 +100,17 @@
u_int32_t ast_ant_txswitch; /* tx antenna switches */
u_int32_t ast_ant_rx[8]; /* rx frames with antenna */
u_int32_t ast_ant_tx[8]; /* tx frames with antenna */
+
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ /* jyyoo add to debug function call frequencies */
+ u_int32_t ast_jyd_ath_hardstart;
+ u_int32_t ast_jyd_ath_hardstart_drop;
+ u_int32_t ast_jyd_ath_hardstart_silent_drop;
+ u_int32_t ast_jyd_ath_hardstart_raw;
+ u_int32_t ast_jyd_ieee80211_hardstart;
+ u_int32_t ast_jyd_ieee80211_hardstart_drop;
+ u_int32_t ast_jyd_ieee80211_hardstart_silent_drop;
+#endif
};

struct ath_diag {
@@ -120,6 +133,22 @@
#define SIOCGATHSTATS (SIOCDEVPRIVATE+0)
#define SIOCGATHDIAG (SIOCDEVPRIVATE+1)
#define SIOCGATHRADARSIG (SIOCDEVPRIVATE+2)
+// jyyoo : buffer len
+#define SIOCSATHBUFLEN (SIOCDEVPRIVATE+3)
+#define SIOCGATHBUFLEN (SIOCDEVPRIVATE+4)
+// jyyoo : in kernel network monitoring
+#define SIOCSATHIKNM (SIOCDEVPRIVATE+5)
+#define SIOCGATHIKNM (SIOCDEVPRIVATE+6)
+// jyyoo : add for per-flow monitoring
+#define SIOCGPFMS_SIGNAL (SIOCDEVPRIVATE+10)
+#define SIOCGPFMS (SIOCDEVPRIVATE+11)
+// jyyoo : add for TTL-based packet filtering
+#define SIOCSTTLPACKETFILTER (SIOCDEVPRIVATE+12)
+#define SIOCGTTLPACKETFILTER (SIOCDEVPRIVATE+13)
+// jyyoo : add for adhoc edca
+#define SIOCSADHOCEDCA (SIOCDEVPRIVATE+14)
+#define SIOCGADHOCEDCA (SIOCDEVPRIVATE+15)
+
#else
#define SIOCGATHSTATS _IOWR('i', 137, struct ifreq)
#define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag)
diff -Nru madwifi-original/ath/if_athvar.h madwifi-new/ath/if_athvar.h
--- madwifi-original/ath/if_athvar.h 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/ath/if_athvar.h 2009-10-15 12:37:28.000000000 +0200
@@ -47,9 +47,17 @@
#include "ah_os.h"
#include "if_athioctl.h"
#include
+#include
#include "net80211/ieee80211.h" /* XXX for WME_NUM_AC */
#include
#include
+#include /* for in_aton */
+#include
+#include
+#include
+#include
+#include
+
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,15)
# include
#endif
@@ -58,6 +66,7 @@
#define irqs_disabled() 0
#endif

+
/*
* Deduce if tasklets are available. If not then
* fall back to using the immediate work queue.
@@ -596,6 +605,34 @@
(_tqs)->axq_link = NULL; \
} while (0)

+
+/* jyyoo (jaeyong): in-kernel-network-monitoring */
+#define HEADER_LEN 76
+struct monitor_param {
+ int sec;
+ int msec;
+ u_int8_t qlen[4];
+ u_int8_t ret;
+ u_int8_t err;
+ u_int8_t modRate;
+ u_int8_t reserved;
+ char header[HEADER_LEN]; /* including ethernet, ip, tcp (+option) header */
+};
+/* MAX_MPARAM basically determines the tradeoff between cpu efficiency and memory efficiency */
+#define HEADER_LEN 76
+struct monitor_param_recv {
+ int sec;
+ int msec;
+ char header[HEADER_LEN]; /* including ethernet, ip, tcp (+option) header */
+};
+/* MAX_MPARAM basically determines the tradeoff between cpu efficiency and memory efficiency */
+/* we use 8KB as the buffer for exchanging the header from process context of outgoing packet and kernel thread */
+/* 8192 / 92 = 85 */
+#define MAX_MPARAM 85
+/* 1440 / 92 = 15 */
+#define MAX_MPARAM_PERPACKET 15
+
+
/*
* concat buffers from one queue to other
*/
@@ -839,6 +876,59 @@
* detected radars */
u_int32_t sc_nexttbtt;
u_int64_t sc_last_tsf;
+
+ /* jyyoo (jaeyong): in-kernel-network-monitor */
+ struct socket* sc_recv_sock_mclient; /* monitor client */
+ int sc_recv_port_number; /* server port */
+ struct sockaddr_in sc_recv_serv_addr; /* server ip address */
+ struct iovec sc_recv_iov_msg; /* message structure */
+ struct msghdr sc_recv_msghdr; /* message header structure */
+ char sc_recv_msgbuf[1440];
+
+ struct sockaddr_in sc_recv_serv_addr2; /* server ip address */
+
+ /* kernel thread for sending the network info to server */
+ struct task_struct* sc_recv_kthread_send;
+ wait_queue_head_t sc_recv_queue_send;
+ int sc_recv_kthread_send_alive;
+
+ /* buffer for sharing between kernel thread and the process of outgoing packet */
+ struct monitor_param_recv sc_recv_monitor_param[MAX_MPARAM];
+ int sc_recv_monitor_head;
+ int sc_recv_monitor_tail;
+
+ spinlock_t sc_recv_send_lock;
+ /* jyyoo (jaeyong): in-kernel-network-monitor */
+ struct socket* sc_sock_mclient; /* monitor client */
+ int sc_port_number; /* server port */
+ struct sockaddr_in sc_serv_addr; /* server ip address */
+ struct iovec sc_iov_msg; /* message structure */
+ struct msghdr sc_msghdr; /* message header structure */
+ char sc_msgbuf[1440];
+
+ struct sockaddr_in sc_serv_addr2; /* server ip address */
+
+ /* kernel thread for sending the network info to server */
+ struct task_struct* sc_kthread_send;
+ wait_queue_head_t sc_queue_send;
+ int sc_kthread_send_alive;
+
+ /* buffer for sharing between kernel thread and the process of outgoing packet */
+ struct monitor_param sc_monitor_param[MAX_MPARAM];
+ int sc_monitor_head;
+ int sc_monitor_tail;
+
+ spinlock_t sc_send_lock;
+
+ /* jyyoo (jaeyong): control tx queue len */
+ int sc_queue_len;
+
+ /* debugging param */
+ int dp_exchange_buffer_drop;
+
+ /* in-kernel-network-monitor enable/disable toggle */
+ int sc_iknm_enable;
+
};

typedef void (*ath_callback) (struct ath_softc *);
diff -Nru madwifi-original/net80211/ieee80211_output.c madwifi-new/net80211/ieee80211_output.c
--- madwifi-original/net80211/ieee80211_output.c 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/net80211/ieee80211_output.c 2009-10-16 23:23:00.000000000 +0200
@@ -53,6 +53,8 @@
#include "if_ethersubr.h"
#include "if_media.h"

+#include
+
#include
#include
#include
@@ -84,13 +86,22 @@
{
struct ieee80211vap *vap = ni->ni_vap;
struct ether_header *eh = (struct ether_header *) skb->data;
+ struct ieee80211com *ic = ni->ni_ic;
int v_wme_ac = 0, d_wme_ac = 0;

/* default priority */
skb->priority = WME_AC_BE;

- if (!(ni->ni_flags & IEEE80211_NODE_QOS))
- return 0;
+ /* jyyoo add to enable ad-hoc edca */
+
+ if( !ic->ic_adhoc_edca )
+ {
+ if (!(ni->ni_flags & IEEE80211_NODE_QOS))
+ return 0;
+ }
+
+ /* jyyoo end */
+

/*
* If node has a vlan tag then all traffic
@@ -111,7 +122,8 @@
ni->ni_stats.ns_tx_vlanmismatch++;
return 1;
}
- if (ni->ni_flags & IEEE80211_NODE_QOS) {
+ if (ni->ni_flags & IEEE80211_NODE_QOS || ic->ic_adhoc_edca) {
+
v_pri = (tag >> VLAN_PRI_SHIFT) & VLAN_PRI_MASK;
switch (v_pri) {
case 1:
@@ -206,6 +218,7 @@
struct net_device *parent = ic->ic_dev;
struct ieee80211_node *ni = NULL;
struct ether_header *eh;
+ int re=0;

/* reset the skb of new frames reaching this layer BEFORE
* we invoke ieee80211_skb_track. */
@@ -230,10 +243,43 @@
#endif
goto bad;
}
+
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ /* jyyoo to debug function call frequencies */
+ {
+ struct net_device* parent_dev = vap->iv_ic->ic_dev;
+ struct ath_softc* sc = parent_dev->priv;
+ sc->sc_stats.ast_jyd_ieee80211_hardstart ++;
+ }
+#endif
+
+ /*
+ * jyyoo : hack to support click
+ * desc: click user-level do not filter the local output packet properly
+ * because iptables can not filter the local output
+ * appropriately. if we use iptables to filter the local
+ * ouput packet, then all the click packets are also filtered out.
+ * The trick is as follows:
+ * ip uses default ttl as IPDEFTTL (64). We filter out ttl of IPDEFTTL (64)
+ * and use pass packets with ttl IPDEFTTL -1 (63). the local packet of ttl IPDEFTTL (64)
+ * will be filtered and we can manually decrease the ttl.
+ */
+ if( ic->ic_enable_ttl_pf )
+ {
+ const struct iphdr *ip = (struct iphdr *)
+ (skb->data + sizeof (struct ether_header));
+ if( ip->version == IPVERSION && ip->ttl == IPDEFTTL )
+ {
+ printk("JYD: packet filtered\n");
+ goto bad;
+ }
+ }
+ /* jyyoo finish */
+

if (vap->iv_opmode == IEEE80211_M_MONITOR) {
ieee80211_monitor_encap(vap, skb);
- ieee80211_parent_queue_xmit(skb);
+ re = ieee80211_parent_queue_xmit(skb);
return NETDEV_TX_OK;
}

@@ -296,15 +342,50 @@
SKB_CB(skb1)->ni = ieee80211_find_txnode(vap->iv_xrvap,
eh->ether_dhost);
/* Ignore this return code. */
- ieee80211_parent_queue_xmit(skb1);
+ re = ieee80211_parent_queue_xmit(skb1);
}
}
#endif
ieee80211_unref_node(&ni);
- ieee80211_parent_queue_xmit(skb);
+ re = ieee80211_parent_queue_xmit(skb);
+
+ if( re == 1 )
+ {
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ /* jyyoo to debug function call frequencies */
+ {
+ struct net_device* parent_dev = vap->iv_ic->ic_dev;
+ struct ath_softc* sc = parent_dev->priv;
+ sc->sc_stats.ast_jyd_ieee80211_hardstart_drop ++;
+ }
+#endif
+
+ /* jyyoo : note
+ * to make the complete driver, we have to stop
+ * queue a bit and wake when it is avilable,
+ * currently, not figured when we have to wake
+ * the queue (netif_wake_queue).
+ * It is probably related when ath(wifi0)-buffer
+ * is sufficiently drained out
+ */
+ // netif_stop_queue(dev);
+
+ //return NETDEV_TX_BUSY;
+ // ENOUBUFS will be directly delivered to raw socket send function
+ return -ENOBUFS;
+ }
return NETDEV_TX_OK;

bad:
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ /* jyyoo to debug function call frequencies */
+ {
+ struct net_device* parent_dev = vap->iv_ic->ic_dev;
+ struct ath_softc* sc = parent_dev->priv;
+ sc->sc_stats.ast_jyd_ieee80211_hardstart_silent_drop ++;
+ }
+#endif
+
if (skb != NULL)
ieee80211_dev_kfree_skb(&skb);
if (ni != NULL)
@@ -316,8 +397,9 @@
* skb is consumed in all cases
*/

-void ieee80211_parent_queue_xmit(struct sk_buff *skb) {
+int ieee80211_parent_queue_xmit(struct sk_buff *skb) {
struct ieee80211vap *vap = skb->dev->priv;
+ int re=0;

vap->iv_devstats.tx_packets++;
vap->iv_devstats.tx_bytes += skb->len;
@@ -327,9 +409,18 @@
skb->dev = vap->iv_ic->ic_dev;

if (netif_queue_stopped(skb->dev))
- ieee80211_dev_kfree_skb(&skb);
+ {
+ vap->iv_devstats.tx_dropped++;
+ re=1;
+// ieee80211_dev_kfree_skb(&skb); // jyyoo disabled the code
+ ieee80211_skb_untrack(skb);
+ }
else if (dev_queue_xmit(skb) == NET_XMIT_DROP)
+ {
vap->iv_devstats.tx_dropped++;
+ re=1;
+ }
+ return re;
}

/*
diff -Nru madwifi-original/net80211/ieee80211_proto.h madwifi-new/net80211/ieee80211_proto.h
--- madwifi-original/net80211/ieee80211_proto.h 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/net80211/ieee80211_proto.h 2009-10-14 20:17:08.000000000 +0200
@@ -73,7 +73,7 @@
struct sk_buff *, int, int, u_int64_t);
void ieee80211_sta_pwrsave(struct ieee80211vap *, int);
int ieee80211_hardstart(struct sk_buff *, struct net_device *);
-void ieee80211_parent_queue_xmit(struct sk_buff *);
+int ieee80211_parent_queue_xmit(struct sk_buff *); // jyyoo modify
int ieee80211_send_nulldata(struct ieee80211_node *);
int ieee80211_send_qosnulldata(struct ieee80211_node *, int);
int ieee80211_send_mgmt(struct ieee80211_node *, int, int);
diff -Nru madwifi-original/net80211/ieee80211_var.h madwifi-new/net80211/ieee80211_var.h
--- madwifi-original/net80211/ieee80211_var.h 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/net80211/ieee80211_var.h 2009-10-05 19:48:35.000000000 +0200
@@ -450,6 +450,15 @@
u_int8_t ic_chanchange_tbtt;
u_int8_t ic_chanchange_chan;

+
+ /* jyyoo add: enable to DEFTTL filtering to support user-level click
+ * to be able to filter out the original kernel-generated packets
+ */
+ u_int32_t ic_enable_ttl_pf;
+
+ /* jyyoo add: enable adhoc edca */
+ u_int32_t ic_adhoc_edca;
+
/* Global debug flags applicable to all VAPs */
int ic_debug;
/* used for reference tracking/counting. Nodes are shared between VAPs,
diff -Nru madwifi-original/tools/athstats.c madwifi-new/tools/athstats.c
--- madwifi-original/tools/athstats.c 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/tools/athstats.c 2009-10-15 12:46:31.000000000 +0200
@@ -279,6 +279,17 @@
"phyerr",
"rssi",
"rate");
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ printf(" %8s %8s %8s %8s %8s %8s %8s",
+ "athxmit",
+ "athraw",
+ "athdrop",
+ "athsdrop",
+ "netxmit",
+ "netdrop",
+ "netsdrop"
+ );
+#endif
putchar('\n');
fflush(stdout);
line = 0;
@@ -290,7 +301,7 @@
err(1, ifr.ifr_name);
if (!getifstats(ifr.ifr_name, &icur, &ocur))
err(1, ifr.ifr_name);
- printf("%8lu %8lu %7u %7u %7u %6u %6u %6u %7u %4u %3uM\n",
+ printf("%8lu %8lu %7u %7u %7u %6u %6u %6u %7u %4u %3uM",
(icur - itot) -
(cur.ast_rx_mgt - total.ast_rx_mgt),
ocur - otot,
@@ -303,6 +314,19 @@
cur.ast_rx_phyerr - total.ast_rx_phyerr,
cur.ast_rx_rssi,
rate);
+
+#ifdef JYD_FUNCTION_CALL_FREQUENCY
+ printf("%8lu %8lu %8lu %8lu %8lu %8lu %8lu",
+ cur.ast_jyd_ath_hardstart - total.ast_jyd_ath_hardstart,
+ cur.ast_jyd_ath_hardstart_raw - total.ast_jyd_ath_hardstart_raw,
+ cur.ast_jyd_ath_hardstart_drop - total.ast_jyd_ath_hardstart_drop,
+ cur.ast_jyd_ath_hardstart_silent_drop - total.ast_jyd_ath_hardstart_silent_drop,
+ cur.ast_jyd_ieee80211_hardstart - total.ast_jyd_ieee80211_hardstart,
+ cur.ast_jyd_ieee80211_hardstart_drop - total.ast_jyd_ieee80211_hardstart_drop,
+ cur.ast_jyd_ieee80211_hardstart_silent_drop - total.ast_jyd_ieee80211_hardstart_silent_drop );
+#endif
+
+ printf("\n");
total = cur;
itot = icur;
otot = ocur;
diff -Nru madwifi-original/tools/wlanconfig.c madwifi-new/tools/wlanconfig.c
--- madwifi-original/tools/wlanconfig.c 2009-10-05 17:25:39.000000000 +0200
+++ madwifi-new/tools/wlanconfig.c 2009-10-05 19:54:01.000000000 +0200
@@ -61,6 +61,7 @@
#include "net80211/ieee80211.h"
#include "net80211/ieee80211_crypto.h"
#include "net80211/ieee80211_ioctl.h"
+#include "ath/if_athioctl.h"
#include "do_multi.h"

/*
@@ -201,6 +202,91 @@
err(1, "unknown 'list' option: %s", arg);
} else /* NB: for compatibility */
list_stations(ifname);
+ /* jyyoo (jaeyong) tx queue len control */
+ } else if ( streq(cmd, "command")) {
+ if( argc == 5 )
+ {
+ struct ifreq ifr;
+ int s;
+ s = socket(AF_INET, SOCK_DGRAM, 0);
+ if( s < 0 )
+ err(1, "socket");
+ ifname = argv[1];
+ strncpy(ifr.ifr_name, ifname, sizeof(ifr.ifr_name));
+ if( streq(argv[3], "stxqlen"))
+ {
+ int value=atoi(argv[4]);
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCSATHBUFLEN, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ } else if( streq(argv[3], "setiknm"))
+ {
+ int value=atoi(argv[4]);
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCSATHIKNM, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ }
+ else if (streq(argv[3], "sttlpf"))
+ {
+ int value=atoi(argv[4]);
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCSTTLPACKETFILTER, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ }
+ else if (streq(argv[3], "sadhocedca"))
+ {
+ int value=atoi(argv[4]);
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCSADHOCEDCA, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ }
+ close(s);
+ }
+ else if( argc == 4 )
+ {
+ struct ifreq ifr;
+ int s;
+ s = socket(AF_INET, SOCK_DGRAM, 0);
+ if( s < 0 )
+ err(1, "socket");
+ ifname = argv[1];
+ strncpy(ifr.ifr_name, ifname, sizeof(ifr.ifr_name));
+ if( streq(argv[3], "gtxqlen"))
+ {
+ int value;
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCGATHBUFLEN, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ printf("queue len: %d\n", value);
+ } else if( streq(argv[3], "getiknm"))
+ {
+ int value;
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCGATHIKNM, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ printf("iknm : %d\n", value);
+ }
+ if( streq(argv[3], "gttlpf"))
+ {
+ int value;
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCGTTLPACKETFILTER, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ printf("ttl packet filter mode: %d\n", value);
+ }
+ if( streq(argv[3], "gadhocedca"))
+ {
+ int value;
+ ifr.ifr_data = (caddr_t) &value;
+ if( ioctl(s, SIOCGADHOCEDCA, &ifr) < 0 )
+ err(1, ifr.ifr_name);
+ printf("adhoc edca: %d\n", value);
+ }
+
+ close(s);
+
+ }
+
} else
usage();

@@ -288,6 +374,7 @@
fprintf(stderr, " wlanmode [sta|adhoc|ap|monitor|wds|ahdemo] [bssid | -bssid] [nosbeacon]\n");
fprintf(stderr, "usage: wlanconfig athX destroy\n");
fprintf(stderr, "usage: wlanconfig athX list [active|ap|caps|chan|freq|keys|scan|sta|wme]\n");
+ fprintf(stderr, "usage: wlanconfig wifiX command [ [s|g]ttlpf | [s|g]adhocedca ]\n");
exit(-1);
}