traffic control examples

$ tc qdisc show dev eth5

$ tc class show dev eth5

$ tc qdisc del dev eth5 root

bonus (ethtool


$ ethtool -s eth6 speed 1000 duplux full

$ ethtool -s eth6 speed 100 autoneg off

how to select a package among several similar packages

in case of java, use the following


$ update-alternatives --config java

When you accidentally press Ctrl+S in vim

ctrl+s locks the screen and vim does not take any inputs.

Just press ctrl+q, it will release the lock.

gstreamer good reading sites

gstreamer all plugins list: http://gstreamer.freedesktop.org/documentation/plugins.html

about RTP streaming: http://webcvs.freedesktop.org/gstreamer/gst-plugins-good/gst/rtp/README?view=markup

gstreamer using python http://www.jejik.com/articles/2007/01/streaming_audio_over_tcp_with_python-gstreamer/

various transports and codecs using gstreamer (warning-Not english!) : http://blog.nicolargo.com/2009/02/jai-streame-avec-gstreamer.html

some vlc commandline streaming commands

@ streaming client side

vlc rtp://@:5004 # rtp stream from any source in 5004 port

vlc udp://192.168.1.1:5004 # udp stream from 192.168.1.1 in port 5004

@ streaming server side

vlc --sout udp://192.168.1.2 # udp stream to dst 192.168.1.2

vlc :sout=#rtp{dst=192.168.1.2,port=5004,mux=ts} :no-sout-rtp-sap :no-sout-standard-sap :sout-all :ttl=1 :sout-keep

[Linux] strace: live system call tracing in Linux

original article: http://linuxhelp.blogspot.com/2006/05/strace-very-powerful-troubleshooting.html

Many times I have come across seemingly hopeless situations where a program when compiled and installed in GNU/Linux just fails to run. In such situations after I have tried every trick in the book like searching on the net and posting questions to Linux forums, and still failed to resolve the problem, I turn to the last resort which is trace the output of the misbehaving program. Tracing the output of a program throws up a lot of data which is not usually available when the program is run normally. And in many instances, sifting through this volume of data has proved fruitful in pin pointing the cause of error.

For tracing the system calls of a program, we have a very good tool in strace. What is unique about strace is that, when it is run in conjunction with a program, it outputs all the calls made to the kernel by the program. In many cases, a program may fail because it is unable to open a file or because of insufficient memory. And tracing the output of the program will clearly show the cause of either problem.

The use of strace is quite simple and takes the following form:
$ strace
For example, I can run a trace on 'ls' as follows :
$ strace ls
And this will output a great amount of data on to the screen. If it is hard to keep track of the scrolling mass of data, then there is an option to write the output of strace to a file instead which is done using the -o option. For example,
$ strace -o strace_ls_output.txt ls
... will write all the tracing output of 'ls' to the 'strace_ls_output.txt' file. Now all it requires is to open the file in a text editor and analyze the output to get the necessary clues.

It is common to find a lot of system function calls in the strace output. The most common of them being open(),write(),read(),close() and so on. But the function calls are not limited to these four as you will find many others too.

For example, if you look in the strace output of ls, you will find the following line:
open("/lib/libselinux.so.1", O_RDONLY) = 3
This means that some aspect of ls requires the library module libselinux.so.1 to be present in the /lib folder. And if the library is missing or in a different path, then that aspect of ls which depends on this library will fail to function. The line of code signifies that the opening of the library libselinux.so.1 is successful.

[gcc tip] Function backtrace in the program code

be sure that you link with -rdynamic flag

#include (execinfo.h)

void print_trace()
{
const size_t max_depth = 200;
size_t stack_depth;
void *stack_addrs[max_depth];
char **stack_strings;
int i;

stack_depth = backtrace(stack_addrs, max_depth);
stack_strings = backtrace_symbols(stack_addrs, stack_depth);

for (i = 1; i < stack_depth; i++) {
printf("%s\n", stack_strings[i]);
}

free(stack_strings);
}

For more info. visit http://www.gnu.org/s/hello/manual/libc/Backtraces.html

ctags excluding patterns

ctags --exclude=*.html -R *

example of gst-launch

gst-launch-0.10 filesrc location=/home/yjaeyong/test.mp3 \! decodebin \! fakesink

or if you want to use mad for decoding

gst-launch-0.10 filesrc location=/home/yjaeyong/test.mp3 \! mad \! fakesink

gstreamer manual install

although you install ./configure; make; sudo make install

some libraries (for plugins or elements) are not properly installed

sometimes, better to copy .libs/* into /usr/lib manually or try sudo make install again

no idea why that happens!

ldd; a tool that shows the dependencies of libraries

required libraries to completely install gstreamer-base-elements

in ubuntu

$ sudo apt-get install libasound2-dev libvorbis-dev libogg-dev liborc-0.4-dev libgnomevfs2-dev libvisual-0.4-dev libpango1.0-dev libtheora-dev libv4l-dev

linux kernel docu MSI how to (v2.6.27)

1 The MSI Driver Guide HOWTO
2 Tom L Nguyen tom.l.nguyen[AT]intel[DOT]com
3 10/03/2003
4 Revised Feb 12, 2004 by Martine Silbermann
5 email: Martine.Silbermann[AT]hp[DOT]com
6 Revised Jun 25, 2004 by Tom L Nguyen
7
8 1. About this guide
9
10 This guide describes the basics of Message Signaled Interrupts (MSI),
11 the advantages of using MSI over traditional interrupt mechanisms,
12 and how to enable your driver to use MSI or MSI-X. Also included is
13 a Frequently Asked Questions (FAQ) section.
14
15 1.1 Terminology
16
17 PCI devices can be single-function or multi-function. In either case,
18 when this text talks about enabling or disabling MSI on a "device
19 function," it is referring to one specific PCI device and function and
20 not to all functions on a PCI device (unless the PCI device has only
21 one function).
22
23 2. Copyright 2003 Intel Corporation
24
25 3. What is MSI/MSI-X?
26
27 Message Signaled Interrupt (MSI), as described in the PCI Local Bus
28 Specification Revision 2.3 or later, is an optional feature, and a
29 required feature for PCI Express devices. MSI enables a device function
30 to request service by sending an Inbound Memory Write on its PCI bus to
31 the FSB as a Message Signal Interrupt transaction. Because MSI is
32 generated in the form of a Memory Write, all transaction conditions,
33 such as a Retry, Master-Abort, Target-Abort or normal completion, are
34 supported.
35
36 A PCI device that supports MSI must also support pin IRQ assertion
37 interrupt mechanism to provide backward compatibility for systems that
38 do not support MSI. In systems which support MSI, the bus driver is
39 responsible for initializing the message address and message data of
40 the device function's MSI/MSI-X capability structure during device
41 initial configuration.
42
43 An MSI capable device function indicates MSI support by implementing
44 the MSI/MSI-X capability structure in its PCI capability list. The
45 device function may implement both the MSI capability structure and
46 the MSI-X capability structure; however, the bus driver should not
47 enable both.
48
49 The MSI capability structure contains Message Control register,
50 Message Address register and Message Data register. These registers
51 provide the bus driver control over MSI. The Message Control register
52 indicates the MSI capability supported by the device. The Message
53 Address register specifies the target address and the Message Data
54 register specifies the characteristics of the message. To request
55 service, the device function writes the content of the Message Data
56 register to the target address. The device and its software driver
57 are prohibited from writing to these registers.
58
59 The MSI-X capability structure is an optional extension to MSI. It
60 uses an independent and separate capability structure. There are
61 some key advantages to implementing the MSI-X capability structure
62 over the MSI capability structure as described below.
63
64 - Support a larger maximum number of vectors per function.
65
66 - Provide the ability for system software to configure
67 each vector with an independent message address and message
68 data, specified by a table that resides in Memory Space.
69
70 - MSI and MSI-X both support per-vector masking. Per-vector
71 masking is an optional extension of MSI but a required
72 feature for MSI-X. Per-vector masking provides the kernel the
73 ability to mask/unmask a single MSI while running its
74 interrupt service routine. If per-vector masking is
75 not supported, then the device driver should provide the
76 hardware/software synchronization to ensure that the device
77 generates MSI when the driver wants it to do so.
78
79 4. Why use MSI?
80
81 As a benefit to the simplification of board design, MSI allows board
82 designers to remove out-of-band interrupt routing. MSI is another
83 step towards a legacy-free environment.
84
85 Due to increasing pressure on chipset and processor packages to
86 reduce pin count, the need for interrupt pins is expected to
87 diminish over time. Devices, due to pin constraints, may implement
88 messages to increase performance.
89
90 PCI Express endpoints uses INTx emulation (in-band messages) instead
91 of IRQ pin assertion. Using INTx emulation requires interrupt
92 sharing among devices connected to the same node (PCI bridge) while
93 MSI is unique (non-shared) and does not require BIOS configuration
94 support. As a result, the PCI Express technology requires MSI
95 support for better interrupt performance.
96
97 Using MSI enables the device functions to support two or more
98 vectors, which can be configured to target different CPUs to
99 increase scalability.
100
101 5. Configuring a driver to use MSI/MSI-X
102
103 By default, the kernel will not enable MSI/MSI-X on all devices that
104 support this capability. The CONFIG_PCI_MSI kernel option
105 must be selected to enable MSI/MSI-X support.
106
107 5.1 Including MSI/MSI-X support into the kernel
108
109 To allow MSI/MSI-X capable device drivers to selectively enable
110 MSI/MSI-X (using pci_enable_msi()/pci_enable_msix() as described
111 below), the VECTOR based scheme needs to be enabled by setting
112 CONFIG_PCI_MSI during kernel config.
113
114 Since the target of the inbound message is the local APIC, providing
115 CONFIG_X86_LOCAL_APIC must be enabled as well as CONFIG_PCI_MSI.
116
117 5.2 Configuring for MSI support
118
119 Due to the non-contiguous fashion in vector assignment of the
120 existing Linux kernel, this version does not support multiple
121 messages regardless of a device function is capable of supporting
122 more than one vector. To enable MSI on a device function's MSI
123 capability structure requires a device driver to call the function
124 pci_enable_msi() explicitly.
125
126 5.2.1 API pci_enable_msi
127
128 int pci_enable_msi(struct pci_dev *dev)
129
130 With this new API, a device driver that wants to have MSI
131 enabled on its device function must call this API to enable MSI.
132 A successful call will initialize the MSI capability structure
133 with ONE vector, regardless of whether a device function is
134 capable of supporting multiple messages. This vector replaces the
135 pre-assigned dev->irq with a new MSI vector. To avoid a conflict
136 of the new assigned vector with existing pre-assigned vector requires
137 a device driver to call this API before calling request_irq().
138
139 5.2.2 API pci_disable_msi
140
141 void pci_disable_msi(struct pci_dev *dev)
142
143 This API should always be used to undo the effect of pci_enable_msi()
144 when a device driver is unloading. This API restores dev->irq with
145 the pre-assigned IOAPIC vector and switches a device's interrupt
146 mode to PCI pin-irq assertion/INTx emulation mode.
147
148 Note that a device driver should always call free_irq() on the MSI vector
149 that it has done request_irq() on before calling this API. Failure to do
150 so results in a BUG_ON() and a device will be left with MSI enabled and
151 leaks its vector.
152
153 5.2.3 MSI mode vs. legacy mode diagram
154
155 The below diagram shows the events which switch the interrupt
156 mode on the MSI-capable device function between MSI mode and
157 PIN-IRQ assertion mode.
158
159 ------------ pci_enable_msi ------------------------
160 | | <=============== | |
161 | MSI MODE | | PIN-IRQ ASSERTION MODE |
162 | | ===============> | |
163 ------------ pci_disable_msi ------------------------
164
165
166 Figure 1. MSI Mode vs. Legacy Mode
167
168 In Figure 1, a device operates by default in legacy mode. Legacy
169 in this context means PCI pin-irq assertion or PCI-Express INTx
170 emulation. A successful MSI request (using pci_enable_msi()) switches
171 a device's interrupt mode to MSI mode. A pre-assigned IOAPIC vector
172 stored in dev->irq will be saved by the PCI subsystem and a new
173 assigned MSI vector will replace dev->irq.
174
175 To return back to its default mode, a device driver should always call
176 pci_disable_msi() to undo the effect of pci_enable_msi(). Note that a
177 device driver should always call free_irq() on the MSI vector it has
178 done request_irq() on before calling pci_disable_msi(). Failure to do
179 so results in a BUG_ON() and a device will be left with MSI enabled and
180 leaks its vector. Otherwise, the PCI subsystem restores a device's
181 dev->irq with a pre-assigned IOAPIC vector and marks the released
182 MSI vector as unused.
183
184 Once being marked as unused, there is no guarantee that the PCI
185 subsystem will reserve this MSI vector for a device. Depending on
186 the availability of current PCI vector resources and the number of
187 MSI/MSI-X requests from other drivers, this MSI may be re-assigned.
188
189 For the case where the PCI subsystem re-assigns this MSI vector to
190 another driver, a request to switch back to MSI mode may result
191 in being assigned a different MSI vector or a failure if no more
192 vectors are available.
193
194 5.3 Configuring for MSI-X support
195
196 Due to the ability of the system software to configure each vector of
197 the MSI-X capability structure with an independent message address
198 and message data, the non-contiguous fashion in vector assignment of
199 the existing Linux kernel has no impact on supporting multiple
200 messages on an MSI-X capable device functions. To enable MSI-X on
201 a device function's MSI-X capability structure requires its device
202 driver to call the function pci_enable_msix() explicitly.
203
204 The function pci_enable_msix(), once invoked, enables either
205 all or nothing, depending on the current availability of PCI vector
206 resources. If the PCI vector resources are available for the number
207 of vectors requested by a device driver, this function will configure
208 the MSI-X table of the MSI-X capability structure of a device with
209 requested messages. To emphasize this reason, for example, a device
210 may be capable for supporting the maximum of 32 vectors while its
211 software driver usually may request 4 vectors. It is recommended
212 that the device driver should call this function once during the
213 initialization phase of the device driver.
214
215 Unlike the function pci_enable_msi(), the function pci_enable_msix()
216 does not replace the pre-assigned IOAPIC dev->irq with a new MSI
217 vector because the PCI subsystem writes the 1:1 vector-to-entry mapping
218 into the field vector of each element contained in a second argument.
219 Note that the pre-assigned IOAPIC dev->irq is valid only if the device
220 operates in PIN-IRQ assertion mode. In MSI-X mode, any attempt at
221 using dev->irq by the device driver to request for interrupt service
222 may result in unpredictable behavior.
223
224 For each MSI-X vector granted, a device driver is responsible for calling
225 other functions like request_irq(), enable_irq(), etc. to enable
226 this vector with its corresponding interrupt service handler. It is
227 a device driver's choice to assign all vectors with the same
228 interrupt service handler or each vector with a unique interrupt
229 service handler.
230
231 5.3.1 Handling MMIO address space of MSI-X Table
232
233 The PCI 3.0 specification has implementation notes that MMIO address
234 space for a device's MSI-X structure should be isolated so that the
235 software system can set different pages for controlling accesses to the
236 MSI-X structure. The implementation of MSI support requires the PCI
237 subsystem, not a device driver, to maintain full control of the MSI-X
238 table/MSI-X PBA (Pending Bit Array) and MMIO address space of the MSI-X
239 table/MSI-X PBA. A device driver is prohibited from requesting the MMIO
240 address space of the MSI-X table/MSI-X PBA. Otherwise, the PCI subsystem
241 will fail enabling MSI-X on its hardware device when it calls the function
242 pci_enable_msix().
243
244 5.3.2 API pci_enable_msix
245
246 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
247
248 This API enables a device driver to request the PCI subsystem
249 to enable MSI-X messages on its hardware device. Depending on
250 the availability of PCI vectors resources, the PCI subsystem enables
251 either all or none of the requested vectors.
252
253 Argument 'dev' points to the device (pci_dev) structure.
254
255 Argument 'entries' is a pointer to an array of msix_entry structs.
256 The number of entries is indicated in argument 'nvec'.
257 struct msix_entry is defined in /driver/pci/msi.h:
258
259 struct msix_entry {
260 u16 vector; /* kernel uses to write alloc vector */
261 u16 entry; /* driver uses to specify entry */
262 };
263
264 A device driver is responsible for initializing the field 'entry' of
265 each element with a unique entry supported by MSI-X table. Otherwise,
266 -EINVAL will be returned as a result. A successful return of zero
267 indicates the PCI subsystem completed initializing each of the requested
268 entries of the MSI-X table with message address and message data.
269 Last but not least, the PCI subsystem will write the 1:1
270 vector-to-entry mapping into the field 'vector' of each element. A
271 device driver is responsible for keeping track of allocated MSI-X
272 vectors in its internal data structure.
273
274 A return of zero indicates that the number of MSI-X vectors was
275 successfully allocated. A return of greater than zero indicates
276 MSI-X vector shortage. Or a return of less than zero indicates
277 a failure. This failure may be a result of duplicate entries
278 specified in second argument, or a result of no available vector,
279 or a result of failing to initialize MSI-X table entries.
280
281 5.3.3 API pci_disable_msix
282
283 void pci_disable_msix(struct pci_dev *dev)
284
285 This API should always be used to undo the effect of pci_enable_msix()
286 when a device driver is unloading. Note that a device driver should
287 always call free_irq() on all MSI-X vectors it has done request_irq()
288 on before calling this API. Failure to do so results in a BUG_ON() and
289 a device will be left with MSI-X enabled and leaks its vectors.
290
291 5.3.4 MSI-X mode vs. legacy mode diagram
292
293 The below diagram shows the events which switch the interrupt
294 mode on the MSI-X capable device function between MSI-X mode and
295 PIN-IRQ assertion mode (legacy).
296
297 ------------ pci_enable_msix(,,n) ------------------------
298 | | <=============== | |
299 | MSI-X MODE | | PIN-IRQ ASSERTION MODE |
300 | | ===============> | |
301 ------------ pci_disable_msix ------------------------
302
303 Figure 2. MSI-X Mode vs. Legacy Mode
304
305 In Figure 2, a device operates by default in legacy mode. A
306 successful MSI-X request (using pci_enable_msix()) switches a
307 device's interrupt mode to MSI-X mode. A pre-assigned IOAPIC vector
308 stored in dev->irq will be saved by the PCI subsystem; however,
309 unlike MSI mode, the PCI subsystem will not replace dev->irq with
310 assigned MSI-X vector because the PCI subsystem already writes the 1:1
311 vector-to-entry mapping into the field 'vector' of each element
312 specified in second argument.
313
314 To return back to its default mode, a device driver should always call
315 pci_disable_msix() to undo the effect of pci_enable_msix(). Note that
316 a device driver should always call free_irq() on all MSI-X vectors it
317 has done request_irq() on before calling pci_disable_msix(). Failure
318 to do so results in a BUG_ON() and a device will be left with MSI-X
319 enabled and leaks its vectors. Otherwise, the PCI subsystem switches a
320 device function's interrupt mode from MSI-X mode to legacy mode and
321 marks all allocated MSI-X vectors as unused.
322
323 Once being marked as unused, there is no guarantee that the PCI
324 subsystem will reserve these MSI-X vectors for a device. Depending on
325 the availability of current PCI vector resources and the number of
326 MSI/MSI-X requests from other drivers, these MSI-X vectors may be
327 re-assigned.
328
329 For the case where the PCI subsystem re-assigned these MSI-X vectors
330 to other drivers, a request to switch back to MSI-X mode may result
331 being assigned with another set of MSI-X vectors or a failure if no
332 more vectors are available.
333
334 5.4 Handling function implementing both MSI and MSI-X capabilities
335
336 For the case where a function implements both MSI and MSI-X
337 capabilities, the PCI subsystem enables a device to run either in MSI
338 mode or MSI-X mode but not both. A device driver determines whether it
339 wants MSI or MSI-X enabled on its hardware device. Once a device
340 driver requests for MSI, for example, it is prohibited from requesting
341 MSI-X; in other words, a device driver is not permitted to ping-pong
342 between MSI mod MSI-X mode during a run-time.
343
344 5.5 Hardware requirements for MSI/MSI-X support
345
346 MSI/MSI-X support requires support from both system hardware and
347 individual hardware device functions.
348
349 5.5.1 Required x86 hardware support
350
351 Since the target of MSI address is the local APIC CPU, enabling
352 MSI/MSI-X support in the Linux kernel is dependent on whether existing
353 system hardware supports local APIC. Users should verify that their
354 system supports local APIC operation by testing that it runs when
355 CONFIG_X86_LOCAL_APIC=y.
356
357 In SMP environment, CONFIG_X86_LOCAL_APIC is automatically set;
358 however, in UP environment, users must manually set
359 CONFIG_X86_LOCAL_APIC. Once CONFIG_X86_LOCAL_APIC=y, setting
360 CONFIG_PCI_MSI enables the VECTOR based scheme and the option for
361 MSI-capable device drivers to selectively enable MSI/MSI-X.
362
363 Note that CONFIG_X86_IO_APIC setting is irrelevant because MSI/MSI-X
364 vector is allocated new during runtime and MSI/MSI-X support does not
365 depend on BIOS support. This key independency enables MSI/MSI-X
366 support on future IOxAPIC free platforms.
367
368 5.5.2 Device hardware support
369
370 The hardware device function supports MSI by indicating the
371 MSI/MSI-X capability structure on its PCI capability list. By
372 default, this capability structure will not be initialized by
373 the kernel to enable MSI during the system boot. In other words,
374 the device function is running on its default pin assertion mode.
375 Note that in many cases the hardware supporting MSI have bugs,
376 which may result in system hangs. The software driver of specific
377 MSI-capable hardware is responsible for deciding whether to call
378 pci_enable_msi or not. A return of zero indicates the kernel
379 successfully initialized the MSI/MSI-X capability structure of the
380 device function. The device function is now running on MSI/MSI-X mode.
381
382 5.6 How to tell whether MSI/MSI-X is enabled on device function
383
384 At the driver level, a return of zero from the function call of
385 pci_enable_msi()/pci_enable_msix() indicates to a device driver that
386 its device function is initialized successfully and ready to run in
387 MSI/MSI-X mode.
388
389 At the user level, users can use the command 'cat /proc/interrupts'
390 to display the vectors allocated for devices and their interrupt
391 MSI/MSI-X modes ("PCI-MSI"/"PCI-MSI-X"). Below shows MSI mode is
392 enabled on a SCSI Adaptec 39320D Ultra320 controller.
393
394 CPU0 CPU1
395 0: 324639 0 IO-APIC-edge timer
396 1: 1186 0 IO-APIC-edge i8042
397 2: 0 0 XT-PIC cascade
398 12: 2797 0 IO-APIC-edge i8042
399 14: 6543 0 IO-APIC-edge ide0
400 15: 1 0 IO-APIC-edge ide1
401 169: 0 0 IO-APIC-level uhci-hcd
402 185: 0 0 IO-APIC-level uhci-hcd
403 193: 138 10 PCI-MSI aic79xx
404 201: 30 0 PCI-MSI aic79xx
405 225: 30 0 IO-APIC-level aic7xxx
406 233: 30 0 IO-APIC-level aic7xxx
407 NMI: 0 0
408 LOC: 324553 325068
409 ERR: 0
410 MIS: 0
411
412 6. MSI quirks
413
414 Several PCI chipsets or devices are known to not support MSI.
415 The PCI stack provides 3 possible levels of MSI disabling:
416 * on a single device
417 * on all devices behind a specific bridge
418 * globally
419
420 6.1. Disabling MSI on a single device
421
422 Under some circumstances it might be required to disable MSI on a
423 single device. This may be achieved by either not calling pci_enable_msi()
424 or all, or setting the pci_dev->no_msi flag before (most of the time
425 in a quirk).
426
427 6.2. Disabling MSI below a bridge
428
429 The vast majority of MSI quirks are required by PCI bridges not
430 being able to route MSI between busses. In this case, MSI have to be
431 disabled on all devices behind this bridge. It is achieves by setting
432 the PCI_BUS_FLAGS_NO_MSI flag in the pci_bus->bus_flags of the bridge
433 subordinate bus. There is no need to set the same flag on bridges that
434 are below the broken bridge. When pci_enable_msi() is called to enable
435 MSI on a device, pci_msi_supported() takes care of checking the NO_MSI
436 flag in all parent busses of the device.
437
438 Some bridges actually support dynamic MSI support enabling/disabling
439 by changing some bits in their PCI configuration space (especially
440 the Hypertransport chipsets such as the nVidia nForce and Serverworks
441 HT2000). It may then be required to update the NO_MSI flag on the
442 corresponding devices in the sysfs hierarchy. To enable MSI support
443 on device "0000:00:0e", do:
444
445 echo 1 > /sys/bus/pci/devices/0000:00:0e/msi_bus
446
447 To disable MSI support, echo 0 instead of 1. Note that it should be
448 used with caution since changing this value might break interrupts.
449
450 6.3. Disabling MSI globally
451
452 Some extreme cases may require to disable MSI globally on the system.
453 For now, the only known case is a Serverworks PCI-X chipsets (MSI are
454 not supported on several busses that are not all connected to the
455 chipset in the Linux PCI hierarchy). In the vast majority of other
456 cases, disabling only behind a specific bridge is enough.
457
458 For debugging purpose, the user may also pass pci=nomsi on the kernel
459 command-line to explicitly disable MSI globally. But, once the appro-
460 priate quirks are added to the kernel, this option should not be
461 required anymore.
462
463 6.4. Finding why MSI cannot be enabled on a device
464
465 Assuming that MSI are not enabled on a device, you should look at
466 dmesg to find messages that quirks may output when disabling MSI
467 on some devices, some bridges or even globally.
468 Then, lspci -t gives the list of bridges above a device. Reading
469 /sys/bus/pci/devices/0000:00:0e/msi_bus will tell you whether MSI
470 are enabled (1) or disabled (0). In 0 is found in a single bridge
471 msi_bus file above the device, MSI cannot be enabled.
472
473 7. FAQ
474
475 Q1. Are there any limitations on using the MSI?
476
477 A1. If the PCI device supports MSI and conforms to the
478 specification and the platform supports the APIC local bus,
479 then using MSI should work.
480
481 Q2. Will it work on all the Pentium processors (P3, P4, Xeon,
482 AMD processors)? In P3 IPI's are transmitted on the APIC local
483 bus and in P4 and Xeon they are transmitted on the system
484 bus. Are there any implications with this?
485
486 A2. MSI support enables a PCI device sending an inbound
487 memory write (0xfeexxxxx as target address) on its PCI bus
488 directly to the FSB. Since the message address has a
489 redirection hint bit cleared, it should work.
490
491 Q3. The target address 0xfeexxxxx will be translated by the
492 Host Bridge into an interrupt message. Are there any
493 limitations on the chipsets such as Intel 8xx, Intel e7xxx,
494 or VIA?
495
496 A3. If these chipsets support an inbound memory write with
497 target address set as 0xfeexxxxx, as conformed to PCI
498 specification 2.3 or latest, then it should work.
499
500 Q4. From the driver point of view, if the MSI is lost because
501 of errors occurring during inbound memory write, then it may
502 wait forever. Is there a mechanism for it to recover?
503
504 A4. Since the target of the transaction is an inbound memory
505 write, all transaction termination conditions (Retry,
506 Master-Abort, Target-Abort, or normal completion) are
507 supported. A device sending an MSI must abide by all the PCI
508 rules and conditions regarding that inbound memory write. So,
509 if a retry is signaled it must retry, etc... We believe that
510 the recommendation for Abort is also a retry (refer to PCI
511 specification 2.3 or latest).

linux kernel docu dma how to (v3.1)

        Dynamic DMA mapping Guide         =========================       David S. Miller      Richard Henderson       Jakub Jelinek     This is a guide to device driver writers on how to use the DMA API  with example pseudo-code.  For a concise description of the API, see  DMA-API.txt.    Most of the 64bit platforms have special hardware that translates bus  addresses (DMA addresses) into physical addresses.  This is similar to  how page tables and/or a TLB translates virtual addresses to physical  addresses on a CPU.  This is needed so that e.g. PCI devices can  access with a Single Address Cycle (32bit DMA address) any page in the  64bit physical address space.  Previously in Linux those 64bit  platforms had to set artificial limits on the maximum RAM size in the  system, so that the virt_to_bus() static scheme works (the DMA address  translation tables were simply filled on bootup to map each bus  address to the physical page __pa(bus_to_virt())).    So that Linux can use the dynamic DMA mapping, it needs some help from the  drivers, namely it has to take into account that DMA addresses should be  mapped only for the time they are actually used and unmapped after the DMA  transfer.    The following API will work of course even on platforms where no such  hardware exists.    Note that the DMA API works with any bus independent of the underlying  microprocessor architecture. You should use the DMA API rather than  the bus specific DMA API (e.g. pci_dma_*).    First of all, you should make sure    #include     is in your driver. This file will obtain for you the definition of the  dma_addr_t (which can hold any valid DMA address for the platform)  type which should be used everywhere you hold a DMA (bus) address  returned from the DMA mapping functions.        What memory is DMA'able?    The first piece of information you must know is what kernel memory can  be used with the DMA mapping facilities.  There has been an unwritten  set of rules regarding this, and this text is an attempt to finally  write them down.    If you acquired your memory via the page allocator  (i.e. __get_free_page*()) or the generic memory allocators  (i.e. kmalloc() or kmem_cache_alloc()) then you may DMA to/from  that memory using the addresses returned from those routines.    This means specifically that you may _not_ use the memory/addresses  returned from vmalloc() for DMA.  It is possible to DMA to the  _underlying_ memory mapped into a vmalloc() area, but this requires  walking page tables to get the physical addresses, and then  translating each of those pages back to a kernel address using  something like __va().  [ EDIT: Update this when we integrate  Gerd Knorr's generic code which does this. ]    This rule also means that you may use neither kernel image addresses  (items in data/text/bss segments), nor module image addresses, nor  stack addresses for DMA.  These could all be mapped somewhere entirely  different than the rest of physical memory.  Even if those classes of  memory could physically work with DMA, you'd need to ensure the I/O  buffers were cacheline-aligned.  Without that, you'd see cacheline  sharing problems (data corruption) on CPUs with DMA-incoherent caches.  (The CPU could write to one word, DMA would write to a different one  in the same cache line, and one of them could be overwritten.)    Also, this means that you cannot take the return of a kmap()  call and DMA to/from that.  This is similar to vmalloc().    What about block I/O and networking buffers?  The block I/O and  networking subsystems make sure that the buffers they use are valid  for you to DMA from/to.       DMA addressing limitations    Does your device have any DMA addressing limitations?  For example, is  your device only capable of driving the low order 24-bits of address?  If so, you need to inform the kernel of this fact.    By default, the kernel assumes that your device can address the full  32-bits.  For a 64-bit capable device, this needs to be increased.  And for a device with limitations, as discussed in the previous  paragraph, it needs to be decreased.    Special note about PCI: PCI-X specification requires PCI-X devices to  support 64-bit addressing (DAC) for all transactions.  And at least  one platform (SGI SN2) requires 64-bit consistent allocations to  operate correctly when the IO bus is in PCI-X mode.    For correct operation, you must interrogate the kernel in your device  probe routine to see if the DMA controller on the machine can properly  support the DMA addressing limitation your device has.  It is good  style to do this even if your device holds the default setting,  because this shows that you did think about these issues wrt. your  device.    The query is performed via a call to dma_set_mask():     int dma_set_mask(struct device *dev, u64 mask);    The query for consistent allocations is performed via a call to  dma_set_coherent_mask():     int dma_set_coherent_mask(struct device *dev, u64 mask);    Here, dev is a pointer to the device struct of your device, and mask  is a bit mask describing which bits of an address your device  supports.  It returns zero if your card can perform DMA properly on  the machine given the address mask you provided.  In general, the  device struct of your device is embedded in the bus specific device  struct of your device.  For example, a pointer to the device struct of  your PCI device is pdev->dev (pdev is a pointer to the PCI device  struct of your device).    If it returns non-zero, your device cannot perform DMA properly on  this platform, and attempting to do so will result in undefined  behavior.  You must either use a different mask, or not use DMA.    This means that in the failure case, you have three options:    1) Use another DMA mask, if possible (see below).  2) Use some non-DMA mode for data transfer, if possible.  3) Ignore this device and do not initialize it.    It is recommended that your driver print a kernel KERN_WARNING message  when you end up performing either #2 or #3.  In this manner, if a user  of your driver reports that performance is bad or that the device is not  even detected, you can ask them for the kernel messages to find out  exactly why.    The standard 32-bit addressing device would do something like this:     if (dma_set_mask(dev, DMA_BIT_MASK(32))) {    printk(KERN_WARNING           "mydev: No suitable DMA available.\n");    goto ignore_this_device;   }    Another common scenario is a 64-bit capable device.  The approach here  is to try for 64-bit addressing, but back down to a 32-bit mask that  should not fail.  The kernel may fail the 64-bit mask not because the  platform is not capable of 64-bit addressing.  Rather, it may fail in  this case simply because 32-bit addressing is done more efficiently  than 64-bit addressing.  For example, Sparc64 PCI SAC addressing is  more efficient than DAC addressing.    Here is how you would handle a 64-bit capable device which can drive  all 64-bits when accessing streaming DMA:     int using_dac;     if (!dma_set_mask(dev, DMA_BIT_MASK(64))) {    using_dac = 1;   } else if (!dma_set_mask(dev, DMA_BIT_MASK(32))) {    using_dac = 0;   } else {    printk(KERN_WARNING           "mydev: No suitable DMA available.\n");    goto ignore_this_device;   }    If a card is capable of using 64-bit consistent allocations as well,  the case would look like this:     int using_dac, consistent_using_dac;     if (!dma_set_mask(dev, DMA_BIT_MASK(64))) {    using_dac = 1;       consistent_using_dac = 1;    dma_set_coherent_mask(dev, DMA_BIT_MASK(64));   } else if (!dma_set_mask(dev, DMA_BIT_MASK(32))) {    using_dac = 0;    consistent_using_dac = 0;    dma_set_coherent_mask(dev, DMA_BIT_MASK(32));   } else {    printk(KERN_WARNING           "mydev: No suitable DMA available.\n");    goto ignore_this_device;   }    dma_set_coherent_mask() will always be able to set the same or a  smaller mask as dma_set_mask(). However for the rare case that a  device driver only uses consistent allocations, one would have to  check the return value from dma_set_coherent_mask().    Finally, if your device can only drive the low 24-bits of  address you might do something like:     if (dma_set_mask(dev, DMA_BIT_MASK(24))) {    printk(KERN_WARNING           "mydev: 24-bit DMA addressing not available.\n");    goto ignore_this_device;   }    When dma_set_mask() is successful, and returns zero, the kernel saves  away this mask you have provided.  The kernel will use this  information later when you make DMA mappings.    There is a case which we are aware of at this time, which is worth  mentioning in this documentation.  If your device supports multiple  functions (for example a sound card provides playback and record  functions) and the various different functions have _different_  DMA addressing limitations, you may wish to probe each mask and  only provide the functionality which the machine can handle.  It  is important that the last call to dma_set_mask() be for the  most specific mask.    Here is pseudo-code showing how this might be done:     #define PLAYBACK_ADDRESS_BITS DMA_BIT_MASK(32)   #define RECORD_ADDRESS_BITS DMA_BIT_MASK(24)     struct my_sound_card *card;   struct device *dev;     ...   if (!dma_set_mask(dev, PLAYBACK_ADDRESS_BITS)) {    card->playback_enabled = 1;   } else {    card->playback_enabled = 0;    printk(KERN_WARNING "%s: Playback disabled due to DMA limitations.\n",           card->name);   }   if (!dma_set_mask(dev, RECORD_ADDRESS_BITS)) {    card->record_enabled = 1;   } else {    card->record_enabled = 0;    printk(KERN_WARNING "%s: Record disabled due to DMA limitations.\n",           card->name);   }    A sound card was used as an example here because this genre of PCI  devices seems to be littered with ISA chips given a PCI front end,  and thus retaining the 16MB DMA addressing limitations of ISA.       Types of DMA mappings    There are two types of DMA mappings:    - Consistent DMA mappings which are usually mapped at driver    initialization, unmapped at the end and for which the hardware should    guarantee that the device and the CPU can access the data    in parallel and will see updates made by each other without any    explicit software flushing.      Think of "consistent" as "synchronous" or "coherent".      The current default is to return consistent memory in the low 32    bits of the bus space.  However, for future compatibility you should    set the consistent mask even if this default is fine for your    driver.      Good examples of what to use consistent mappings for are:     - Network card DMA ring descriptors.   - SCSI adapter mailbox command data structures.   - Device firmware microcode executed out of     main memory.      The invariant these examples all require is that any CPU store    to memory is immediately visible to the device, and vice    versa.  Consistent mappings guarantee this.      IMPORTANT: Consistent DMA memory does not preclude the usage of               proper memory barriers.  The CPU may reorder stores to        consistent memory just as it may normal memory.  Example:        if it is important for the device to see the first word        of a descriptor updated before the second, you must do        something like:      desc->word0 = address;    wmb();    desc->word1 = DESC_VALID;                 in order to get correct behavior on all platforms.          Also, on some platforms your driver may need to flush CPU write        buffers in much the same way as it needs to flush write buffers        found in PCI bridges (such as by reading a register's value        after writing it).    - Streaming DMA mappings which are usually mapped for one DMA    transfer, unmapped right after it (unless you use dma_sync_* below)    and for which hardware can optimize for sequential accesses.      This of "streaming" as "asynchronous" or "outside the coherency    domain".      Good examples of what to use streaming mappings for are:     - Networking buffers transmitted/received by a device.   - Filesystem buffers written/read by a SCSI device.      The interfaces for using this type of mapping were designed in    such a way that an implementation can make whatever performance    optimizations the hardware allows.  To this end, when using    such mappings you must be explicit about what you want to happen.    Neither type of DMA mapping has alignment restrictions that come from  the underlying bus, although some devices may have such restrictions.  Also, systems with caches that aren't DMA-coherent will work better  when the underlying buffers don't share cache lines with other data.         Using Consistent DMA mappings.    To allocate and map large (PAGE_SIZE or so) consistent DMA regions,  you should do:     dma_addr_t dma_handle;     cpu_addr = dma_alloc_coherent(dev, size, &dma_handle, gfp);    where device is a struct device *. This may be called in interrupt  context with the GFP_ATOMIC flag.    Size is the length of the region you want to allocate, in bytes.    This routine will allocate RAM for that region, so it acts similarly to  __get_free_pages (but takes size instead of a page order).  If your  driver needs regions sized smaller than a page, you may prefer using  the dma_pool interface, described below.    The consistent DMA mapping interfaces, for non-NULL dev, will by  default return a DMA address which is 32-bit addressable.  Even if the  device indicates (via DMA mask) that it may address the upper 32-bits,  consistent allocation will only return > 32-bit addresses for DMA if  the consistent DMA mask has been explicitly changed via  dma_set_coherent_mask().  This is true of the dma_pool interface as  well.    dma_alloc_coherent returns two values: the virtual address which you  can use to access it from the CPU and dma_handle which you pass to the  card.    The cpu return address and the DMA bus master address are both  guaranteed to be aligned to the smallest PAGE_SIZE order which  is greater than or equal to the requested size.  This invariant  exists (for example) to guarantee that if you allocate a chunk  which is smaller than or equal to 64 kilobytes, the extent of the  buffer you receive will not cross a 64K boundary.    To unmap and free such a DMA region, you call:     dma_free_coherent(dev, size, cpu_addr, dma_handle);    where dev, size are the same as in the above call and cpu_addr and  dma_handle are the values dma_alloc_coherent returned to you.  This function may not be called in interrupt context.    If your driver needs lots of smaller memory regions, you can write  custom code to subdivide pages returned by dma_alloc_coherent,  or you can use the dma_pool API to do that.  A dma_pool is like  a kmem_cache, but it uses dma_alloc_coherent not __get_free_pages.  Also, it understands common hardware constraints for alignment,  like queue heads needing to be aligned on N byte boundaries.    Create a dma_pool like this:     struct dma_pool *pool;     pool = dma_pool_create(name, dev, size, align, alloc);    The "name" is for diagnostics (like a kmem_cache name); dev and size  are as above.  The device's hardware alignment requirement for this  type of data is "align" (which is expressed in bytes, and must be a  power of two).  If your device has no boundary crossing restrictions,  pass 0 for alloc; passing 4096 says memory allocated from this pool  must not cross 4KByte boundaries (but at that time it may be better to  go for dma_alloc_coherent directly instead).    Allocate memory from a dma pool like this:     cpu_addr = dma_pool_alloc(pool, flags, &dma_handle);    flags are SLAB_KERNEL if blocking is permitted (not in_interrupt nor  holding SMP locks), SLAB_ATOMIC otherwise.  Like dma_alloc_coherent,  this returns two values, cpu_addr and dma_handle.    Free memory that was allocated from a dma_pool like this:     dma_pool_free(pool, cpu_addr, dma_handle);    where pool is what you passed to dma_pool_alloc, and cpu_addr and  dma_handle are the values dma_pool_alloc returned. This function  may be called in interrupt context.    Destroy a dma_pool by calling:     dma_pool_destroy(pool);    Make sure you've called dma_pool_free for all memory allocated  from a pool before you destroy the pool. This function may not  be called in interrupt context.       DMA Direction    The interfaces described in subsequent portions of this document  take a DMA direction argument, which is an integer and takes on  one of the following values:     DMA_BIDIRECTIONAL   DMA_TO_DEVICE   DMA_FROM_DEVICE   DMA_NONE    One should provide the exact DMA direction if you know it.    DMA_TO_DEVICE means "from main memory to the device"  DMA_FROM_DEVICE means "from the device to main memory"  It is the direction in which the data moves during the DMA  transfer.    You are _strongly_ encouraged to specify this as precisely  as you possibly can.    If you absolutely cannot know the direction of the DMA transfer,  specify DMA_BIDIRECTIONAL.  It means that the DMA can go in  either direction.  The platform guarantees that you may legally  specify this, and that it will work, but this may be at the  cost of performance for example.    The value DMA_NONE is to be used for debugging.  One can  hold this in a data structure before you come to know the  precise direction, and this will help catch cases where your  direction tracking logic has failed to set things up properly.    Another advantage of specifying this value precisely (outside of  potential platform-specific optimizations of such) is for debugging.  Some platforms actually have a write permission boolean which DMA  mappings can be marked with, much like page protections in the user  program address space.  Such platforms can and do report errors in the  kernel logs when the DMA controller hardware detects violation of the  permission setting.    Only streaming mappings specify a direction, consistent mappings  implicitly have a direction attribute setting of  DMA_BIDIRECTIONAL.    The SCSI subsystem tells you the direction to use in the  'sc_data_direction' member of the SCSI command your driver is  working on.    For Networking drivers, it's a rather simple affair.  For transmit  packets, map/unmap them with the DMA_TO_DEVICE direction  specifier.  For receive packets, just the opposite, map/unmap them  with the DMA_FROM_DEVICE direction specifier.        Using Streaming DMA mappings    The streaming DMA mapping routines can be called from interrupt  context.  There are two versions of each map/unmap, one which will  map/unmap a single memory region, and one which will map/unmap a  scatterlist.    To map a single region, you do:     struct device *dev = &my_dev->dev;   dma_addr_t dma_handle;   void *addr = buffer->ptr;   size_t size = buffer->len;     dma_handle = dma_map_single(dev, addr, size, direction);    and to unmap it:     dma_unmap_single(dev, dma_handle, size, direction);    You should call dma_unmap_single when the DMA activity is finished, e.g.  from the interrupt which told you that the DMA transfer is done.    Using cpu pointers like this for single mappings has a disadvantage,  you cannot reference HIGHMEM memory in this way.  Thus, there is a  map/unmap interface pair akin to dma_{map,unmap}_single.  These  interfaces deal with page/offset pairs instead of cpu pointers.  Specifically:     struct device *dev = &my_dev->dev;   dma_addr_t dma_handle;   struct page *page = buffer->page;   unsigned long offset = buffer->offset;   size_t size = buffer->len;     dma_handle = dma_map_page(dev, page, offset, size, direction);     ...     dma_unmap_page(dev, dma_handle, size, direction);    Here, "offset" means byte offset within the given page.    With scatterlists, you map a region gathered from several regions by:     int i, count = dma_map_sg(dev, sglist, nents, direction);   struct scatterlist *sg;     for_each_sg(sglist, sg, count, i) {    hw_address[i] = sg_dma_address(sg);    hw_len[i] = sg_dma_len(sg);   }    where nents is the number of entries in the sglist.    The implementation is free to merge several consecutive sglist entries  into one (e.g. if DMA mapping is done with PAGE_SIZE granularity, any  consecutive sglist entries can be merged into one provided the first one  ends and the second one starts on a page boundary - in fact this is a huge  advantage for cards which either cannot do scatter-gather or have very  limited number of scatter-gather entries) and returns the actual number  of sg entries it mapped them to. On failure 0 is returned.    Then you should loop count times (note: this can be less than nents times)  and use sg_dma_address() and sg_dma_len() macros where you previously  accessed sg->address and sg->length as shown above.    To unmap a scatterlist, just call:     dma_unmap_sg(dev, sglist, nents, direction);    Again, make sure DMA activity has already finished.    PLEASE NOTE:  The 'nents' argument to the dma_unmap_sg call must be                the _same_ one you passed into the dma_map_sg call,         it should _NOT_ be the 'count' value _returned_ from the                dma_map_sg call.    Every dma_map_{single,sg} call should have its dma_unmap_{single,sg}  counterpart, because the bus address space is a shared resource (although  in some ports the mapping is per each BUS so less devices contend for the  same bus address space) and you could render the machine unusable by eating  all bus addresses.    If you need to use the same streaming DMA region multiple times and touch  the data in between the DMA transfers, the buffer needs to be synced  properly in order for the cpu and device to see the most uptodate and  correct copy of the DMA buffer.    So, firstly, just map it with dma_map_{single,sg}, and after each DMA  transfer call either:     dma_sync_single_for_cpu(dev, dma_handle, size, direction);    or:     dma_sync_sg_for_cpu(dev, sglist, nents, direction);    as appropriate.    Then, if you wish to let the device get at the DMA area again,  finish accessing the data with the cpu, and then before actually  giving the buffer to the hardware call either:     dma_sync_single_for_device(dev, dma_handle, size, direction);    or:     dma_sync_sg_for_device(dev, sglist, nents, direction);    as appropriate.    After the last DMA transfer call one of the DMA unmap routines  dma_unmap_{single,sg}. If you don't touch the data from the first dma_map_*  call till dma_unmap_*, then you don't have to call the dma_sync_*  routines at all.    Here is pseudo code which shows a situation in which you would need  to use the dma_sync_*() interfaces.     my_card_setup_receive_buffer(struct my_card *cp, char *buffer, int len)   {    dma_addr_t mapping;      mapping = dma_map_single(cp->dev, buffer, len, DMA_FROM_DEVICE);      cp->rx_buf = buffer;    cp->rx_len = len;    cp->rx_dma = mapping;      give_rx_buf_to_card(cp);   }     ...     my_card_interrupt_handler(int irq, void *devid, struct pt_regs *regs)   {    struct my_card *cp = devid;      ...    if (read_card_status(cp) == RX_BUF_TRANSFERRED) {     struct my_card_header *hp;       /* Examine the header to see if we wish      * to accept the data.  But synchronize      * the DMA transfer with the CPU first      * so that we see updated contents.      */     dma_sync_single_for_cpu(&cp->dev, cp->rx_dma,        cp->rx_len,        DMA_FROM_DEVICE);       /* Now it is safe to examine the buffer. */     hp = (struct my_card_header *) cp->rx_buf;     if (header_is_ok(hp)) {      dma_unmap_single(&cp->dev, cp->rx_dma, cp->rx_len,         DMA_FROM_DEVICE);      pass_to_upper_layers(cp->rx_buf);      make_and_setup_new_rx_buf(cp);     } else {      /* CPU should not write to       * DMA_FROM_DEVICE-mapped area,       * so dma_sync_single_for_device() is       * not needed here. It would be required       * for DMA_BIDIRECTIONAL mapping if       * the memory was modified.       */      give_rx_buf_to_card(cp);     }    }   }    Drivers converted fully to this interface should not use virt_to_bus any  longer, nor should they use bus_to_virt. Some drivers have to be changed a  little bit, because there is no longer an equivalent to bus_to_virt in the  dynamic DMA mapping scheme - you have to always store the DMA addresses  returned by the dma_alloc_coherent, dma_pool_alloc, and dma_map_single  calls (dma_map_sg stores them in the scatterlist itself if the platform  supports dynamic DMA mapping in hardware) in your driver structures and/or  in the card registers.    All drivers should be using these interfaces with no exceptions.  It  is planned to completely remove virt_to_bus() and bus_to_virt() as  they are entirely deprecated.  Some ports already do not provide these  as it is impossible to correctly support them.       Handling Errors    DMA address space is limited on some architectures and an allocation  failure can be determined by:    - checking if dma_alloc_coherent returns NULL or dma_map_sg returns 0    - checking the returned dma_addr_t of dma_map_single and dma_map_page    by using dma_mapping_error():     dma_addr_t dma_handle;     dma_handle = dma_map_single(dev, addr, size, direction);   if (dma_mapping_error(dev, dma_handle)) {    /*     * reduce current DMA mapping usage,     * delay and try again later or     * reset driver.     */   }    Networking drivers must call dev_kfree_skb to free the socket buffer  and return NETDEV_TX_OK if the DMA mapping fails on the transmit hook  (ndo_start_xmit). This means that the socket buffer is just dropped in  the failure case.    SCSI drivers must return SCSI_MLQUEUE_HOST_BUSY if the DMA mapping  fails in the queuecommand hook. This means that the SCSI subsystem  passes the command to the driver again later.      Optimizing Unmap State Space Consumption    On many platforms, dma_unmap_{single,page}() is simply a nop.  Therefore, keeping track of the mapping address and length is a waste  of space.  Instead of filling your drivers up with ifdefs and the like  to "work around" this (which would defeat the whole purpose of a  portable API) the following facilities are provided.    Actually, instead of describing the macros one by one, we'll  transform some example code.    1) Use DEFINE_DMA_UNMAP_{ADDR,LEN} in state saving structures.     Example, before:     struct ring_state {    struct sk_buff *skb;    dma_addr_t mapping;    __u32 len;   };       after:     struct ring_state {    struct sk_buff *skb;    DEFINE_DMA_UNMAP_ADDR(mapping);    DEFINE_DMA_UNMAP_LEN(len);   };    2) Use dma_unmap_{addr,len}_set to set these values.     Example, before:     ringp->mapping = FOO;   ringp->len = BAR;       after:     dma_unmap_addr_set(ringp, mapping, FOO);   dma_unmap_len_set(ringp, len, BAR);    3) Use dma_unmap_{addr,len} to access these values.     Example, before:     dma_unmap_single(dev, ringp->mapping, ringp->len,      DMA_FROM_DEVICE);       after:     dma_unmap_single(dev,      dma_unmap_addr(ringp, mapping),      dma_unmap_len(ringp, len),      DMA_FROM_DEVICE);    It really should be self-explanatory.  We treat the ADDR and LEN  separately, because it is possible for an implementation to only  need the address in order to perform the unmap operation.       Platform Issues    If you are just writing drivers for Linux and do not maintain  an architecture port for the kernel, you can safely skip down  to "Closing".    1) Struct scatterlist requirements.       Don't invent the architecture specific struct scatterlist; just use     . You need to enable     CONFIG_NEED_SG_DMA_LENGTH if the architecture supports IOMMUs     (including software IOMMU).    2) ARCH_DMA_MINALIGN       Architectures must ensure that kmalloc'ed buffer is     DMA-safe. Drivers and subsystems depend on it. If an architecture     isn't fully DMA-coherent (i.e. hardware doesn't ensure that data in     the CPU cache is identical to data in main memory),     ARCH_DMA_MINALIGN must be set so that the memory allocator     makes sure that kmalloc'ed buffer doesn't share a cache line with     the others. See arch/arm/include/asm/cache.h as an example.       Note that ARCH_DMA_MINALIGN is about DMA memory alignment     constraints. You don't need to worry about the architecture data     alignment constraints (e.g. the alignment constraints about 64-bit     objects).    3) Supporting multiple types of IOMMUs       If your architecture needs to support multiple types of IOMMUs, you     can use include/linux/asm-generic/dma-mapping-common.h. It's a     library to support the DMA API with multiple types of IOMMUs. Lots     of architectures (x86, powerpc, sh, alpha, ia64, microblaze and     sparc) use it. Choose one to see how it can be used. If you need to     support multiple types of IOMMUs in a single system, the example of     x86 or powerpc helps.          Closing    This document, and the API itself, would not be in its current  form without the feedback and suggestions from numerous individuals.  We would like to specifically mention, in no particular order, the  following people:     Russell King    Leo Dagum    Ralf Baechle    Grant Grundler    Jay Estabrook    Thomas Sailer    Andrea Arcangeli    Jens Axboe    David Mosberger-Tang